[TTL] Add block transfer optimization framework with layout analysis#166
Draft
brnorris03 wants to merge 4 commits intobnorris/ttl-dm-kernel-lowering-fuse-sibling-loopsfrom
Draft
[TTL] Add block transfer optimization framework with layout analysis#166brnorris03 wants to merge 4 commits intobnorris/ttl-dm-kernel-lowering-fuse-sibling-loopsfrom
brnorris03 wants to merge 4 commits intobnorris/ttl-dm-kernel-lowering-fuse-sibling-loopsfrom
Conversation
brnorris03
force-pushed
the
bnorris/block-transfers
branch
2 times, most recently
from
6abc94d to
75da024
Compare
brnorris03
force-pushed
the
bnorris/ttl-dm-kernel-lowering-fuse-sibling-loops
branch
from
7be41b3 to
5429a7c
Compare
Analyzes tensor layouts to select optimal DMA strategies: - FullyContiguous (row-major + interleaved): single noc_async_read/write - RowContiguous (row-major + sharded): per-row transfers (TODO: #118) - TileContiguous (tiled): per-tile noc_async_read_tile (current default) New files: - LayoutUtils.h/cpp: ContiguityLevel enum, analyzeLayoutContiguity() - block_transfers.mlir: tests for tiled and row-major layouts The lowering inspects TTNNLayoutAttr to determine if tensors use tiles or scalar elements, then dispatches to the appropriate transfer strategy.
brnorris03
force-pushed
the
bnorris/block-transfers
branch
from
75da024 to
1ad773a
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What?
Adds layout-aware transfer optimization to TTL-to-TTKernel lowering. The lowering analyzes tensor layouts and selects optimal DMA strategies based on data contiguity.
Why?
Block transfers (
noc_async_read/noc_async_write) are more efficient than tile-by-tile transfers for row-major data. This enables faster transfers when data is contiguous in memory.How?
Introduces a
ContiguityLevelclassification:The lowering inspects
TTNNLayoutAttrto determine if the tensor uses tiles or scalar elements, then dispatches to the appropriate transfer strategy.Deferred
How to Test?
Checklist: