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drivers: pinctrl: pinctrl_tt_bh.c: remove rx and tri enable #834

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drivers: pinctrl: pinctrl_tt_bh.c: remove rx and tri enable #834

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57 changes: 0 additions & 57 deletions drivers/pinctrl/pinctrl_tt_bh.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,27 +16,19 @@

#define PINCTRL_TT_BH_BASE_ADDR 0x80030000

#define PINCTRL_TT_BH_GPIO_PAD_TRIEN_CNTL_REG_OFFSET 0x000001A0
#define PINCTRL_TT_BH_GPIO_PAD_PUEN_CNTL_REG_OFFSET 0x000001A4
#define PINCTRL_TT_BH_GPIO_PAD_PDEN_CNTL_REG_OFFSET 0x000001A8
#define PINCTRL_TT_BH_GPIO_PAD_RXEN_CNTL_REG_OFFSET 0x000001AC
#define PINCTRL_TT_BH_GPIO_PAD_DRV_CNTL_LOW_REG_OFFSET 0x000001B0
#define PINCTRL_TT_BH_GPIO2_PAD_TRIEN_CNTL_REG_OFFSET 0x00000240
#define PINCTRL_TT_BH_GPIO2_PAD_PUEN_CNTL_REG_OFFSET 0x00000244
#define PINCTRL_TT_BH_GPIO2_PAD_PDEN_CNTL_REG_OFFSET 0x00000248
#define PINCTRL_TT_BH_GPIO_PAD_DRV_CNTL_HIGH_REG_OFFSET 0x00000250
#define PINCTRL_TT_BH_GPIO2_PAD_RXEN_CNTL_REG_OFFSET 0x0000025C
#define PINCTRL_TT_BH_GPIO2_PAD_DRV_CNTL_LOW_REG_OFFSET 0x00000278
#define PINCTRL_TT_BH_GPIO2_PAD_DRV_CNTL_HIGH_REG_OFFSET 0x0000027C
#define PINCTRL_TT_BH_GPIO3_PAD_TRIEN_CNTL_REG_OFFSET 0x00000580
#define PINCTRL_TT_BH_GPIO3_PAD_PUEN_CNTL_REG_OFFSET 0x00000584
#define PINCTRL_TT_BH_GPIO3_PAD_PDEN_CNTL_REG_OFFSET 0x00000588
#define PINCTRL_TT_BH_GPIO3_PAD_RXEN_CNTL_REG_OFFSET 0x0000058C
#define PINCTRL_TT_BH_GPIO3_PAD_DRV_CNTL_LOW_REG_OFFSET 0x00000590
#define PINCTRL_TT_BH_GPIO4_PAD_PUEN_CNTL_REG_OFFSET 0x000005A4
#define PINCTRL_TT_BH_GPIO4_PAD_PDEN_CNTL_REG_OFFSET 0x000005A8
#define PINCTRL_TT_BH_GPIO4_PAD_TRIEN_CNTL_REG_OFFSET 0x000005A0
#define PINCTRL_TT_BH_GPIO4_PAD_RXEN_CNTL_REG_OFFSET 0x000005AC
#define PINCTRL_TT_BH_GPIO3_PAD_DRV_CNTL_HIGH_REG_OFFSET 0x000005B0
#define PINCTRL_TT_BH_GPIO4_PAD_DRV_CNTL_LOW_REG_OFFSET 0x000005BC
#define PINCTRL_TT_BH_GPIO4_PAD_DRV_CNTL_HIGH_REG_OFFSET 0x000005C0
Expand All @@ -52,10 +44,8 @@ LOG_MODULE_REGISTER(bh_arc_pinctrl, CONFIG_PINCTRL_LOG_LEVEL);
static inline uint32_t pinctrl_tt_bh_pin_to_bank(uint32_t pin);
static inline uint32_t pinctrl_tt_bh_pin_to_idx(uint32_t pin);

static inline uintptr_t pinctrl_tt_bh_trien_reg(uint32_t pin);
static inline uintptr_t pinctrl_tt_bh_puen_reg(uint32_t pin);
static inline uintptr_t pinctrl_tt_bh_pden_reg(uint32_t pin);
static inline uintptr_t pinctrl_tt_bh_rxen_reg(uint32_t pin);
static inline uintptr_t pinctrl_tt_bh_sten_reg(uint32_t pin);

static inline uintptr_t pinctrl_tt_bh_drvs_reg(uint32_t pin);
Expand Down Expand Up @@ -90,16 +80,6 @@ static int pinctrl_tt_bh_set(uint32_t pin, uint32_t func, uint32_t mode)

idx = pinctrl_tt_bh_pin_to_bank(pin);

/* input-enable */
if ((mode & PINCTRL_TT_BH_TRIEN) != 0) {
sys_write32(pinctrl_tt_bh_trien_reg(pin), BIT(idx));

/* input-schmitt-enable */
if ((mode & PINCTRL_TT_BH_STEN) != 0) {
sys_write32(pinctrl_tt_bh_sten_reg(pin), BIT(idx));
}
}

/* bias-pull-up */
if ((mode & PINCTRL_TT_BH_PUEN) != 0) {
sys_write32(pinctrl_tt_bh_puen_reg(pin), BIT(idx));
Expand All @@ -108,11 +88,6 @@ static int pinctrl_tt_bh_set(uint32_t pin, uint32_t func, uint32_t mode)
sys_write32(pinctrl_tt_bh_pden_reg(pin), BIT(idx));
}

/* receive-enable */
if ((mode & PINCTRL_TT_BH_RXEN) != 0) {
sys_write32(pinctrl_tt_bh_rxen_reg(pin), BIT(idx));
}

/* drive-strength */
if (PINCTRL_TT_BH_DRVS(mode) != PINCTRL_TT_BH_DRVS_DFLT) {
sys_write32(pinctrl_tt_bh_drvs_reg(pin), PINCTRL_TT_BH_DRVS(mode)
Expand Down Expand Up @@ -148,22 +123,6 @@ static inline uint32_t pinctrl_tt_bh_pin_to_idx(uint32_t pin)
return pin & BIT_MASK(PINCTRL_TT_BH_PINS_PER_BANK);
}

static inline uintptr_t pinctrl_tt_bh_trien_reg(uint32_t pin)
{
switch (pinctrl_tt_bh_pin_to_bank(pin)) {
case 0:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO_PAD_TRIEN_CNTL_REG_OFFSET;
case 1:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO2_PAD_TRIEN_CNTL_REG_OFFSET;
case 2:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO3_PAD_TRIEN_CNTL_REG_OFFSET;
case 3:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO4_PAD_TRIEN_CNTL_REG_OFFSET;
default:
CODE_UNREACHABLE;
}
}

static inline uintptr_t pinctrl_tt_bh_puen_reg(uint32_t pin)
{
switch (pinctrl_tt_bh_pin_to_bank(pin)) {
Expand Down Expand Up @@ -196,22 +155,6 @@ static inline uintptr_t pinctrl_tt_bh_pden_reg(uint32_t pin)
}
}

static inline uintptr_t pinctrl_tt_bh_rxen_reg(uint32_t pin)
{
switch (pinctrl_tt_bh_pin_to_bank(pin)) {
case 0:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO_PAD_RXEN_CNTL_REG_OFFSET;
case 1:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO2_PAD_RXEN_CNTL_REG_OFFSET;
case 2:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO3_PAD_RXEN_CNTL_REG_OFFSET;
case 3:
return PINCTRL_TT_BH_BASE_ADDR + PINCTRL_TT_BH_GPIO4_PAD_RXEN_CNTL_REG_OFFSET;
default:
CODE_UNREACHABLE;
}
}

static inline uintptr_t pinctrl_tt_bh_sten_reg(uint32_t pin)
{
switch (pinctrl_tt_bh_pin_to_bank(pin)) {
Expand Down
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