Use correct VRAM transfer mode for savestates #203
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We set the high bit of $2115 to 0, which instructs the PPU to increment the VRAM word address after writing the low data byte. However, the DMA transfer writes low bytes first, then high bytes. This means the high byte of the first word of a transfer was being skipped, leading to an occasional glitchy tile. Setting the mode bit to 1 instead fixes the issue.
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Nice. That's probably the bug total mentioned a long time ago but I couldn't make any sense of it at the time. |
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Merged with #202 |
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We set the high bit of
$2115to 0, which instructs the PPU to increment the VRAM word address after writing the low data byte. However, the DMA transfer writes low bytes first, then high bytes. This means the high byte of the first word of a transfer was being skipped, leading to an occasional glitchy tile. Setting the mode bit to 1 instead fixes the issue.