4-Bit NanoProcessor – VHDL FPGA Implementation

Implementation of a 4-bit nanoprocessor with original and extended instruction sets, designed in VHDL and deployed on the BASYS 3 FPGA development board.

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Project Overview

This project implements a modular 4-bit nanoprocessor architecture supporting both the original four-instruction set and an extended set of fourteen instructions.
The design includes a complete ALU, register management, and program control, with synthesis, simulation, and hardware testing performed as part of the CS1050 coursework.

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Key Achievements

• Extended the instruction set from 4 to 14 instructions while maintaining backward compatibility.
• Modular VHDL design with reusable components.
• Verified functionality on BASYS 3 FPGA hardware.
• Full documentation with performance and timing analysis.
• Signed arithmetic with two’s-complement and overflow detection.

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Instruction Set Architecture

Original Instructions (4)

Instruction	Description	Format
MOVI R, d	Move immediate value to register	10 RRR 000 dddd
ADD Ra, Rb	Add registers Ra and Rb	00 RaRaRa RbRbRb 0000
NEG R	Two’s-complement negation	01 RRR 0000000
JZR R, d	Jump if register is zero	11 RRR 0000 ddd

Extended Instructions (14 total)

Instruction	Description	Format
SUB Ra, Rb	Subtract Rb from Ra	00 RaRaRa RbRbRb 0001
AND Ra, Rb	Bitwise AND operation	00 RaRaRa RbRbRb 0010
OR Ra, Rb	Bitwise OR operation	00 RaRaRa RbRbRb 0011
XOR Ra, Rb	Bitwise XOR operation	00 RaRaRa RbRbRb 0100
MUL Ra, Rb	Multiply registers	00 RaRaRa RbRbRb 0101
CMP Ra, Rb	Compare registers (sets flags)	00 RaRaRa RbRbRb 0111

Additional instructions such as shift operations and immediate variants are implemented in
InstructionDecoder_Extended.vhd.

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Performance Metrics

Metric	Original Design	Extended Design
Instructions Supported	4	14
FPGA Slices Used	28	42
Maximum Frequency	85 MHz	75 MHz
Power Consumption	0.8 W	1.2 W

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Project Structure

VHDL-4bit-NanoProcessor-FPGA/
├── Nanoprocessor/
│ ├── ALU.vhd
│ ├── ControlUnit.vhd
│ ├── InstructionDecoder.vhd
│ ├── Multiplexer.vhd
│ ├── ProgramCounter.vhd
│ ├── RegisterBank.vhd
│ └── TopLevel.vhd
├── Nanoprocessor-Extended/
│ ├── ALU_Extended.vhd
│ ├── ControlUnit_Extended.vhd
│ ├── InstructionDecoder_Extended.vhd
│ ├── Multiplexer_Extended.vhd
│ ├── ProgramCounter_Extended.vhd
│ ├── RegisterBank_Extended.vhd
│ └── TopLevel_Extended.vhd
├── Presentation/
│ ├── NanoProcessor_Presentation.pdf
│ └── NanoProcessor_Presentation.pptx
├── NanoProcessor_Project_Report.pdf
├── README.md
└── .gitignore

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Getting Started

Prerequisites

• Xilinx Vivado Design Suite (2020.2 or later recommended)
• Basys 3 FPGA Board (Artix-7)

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Setup and Synthesis

git clone https://github.com/HimathX/VHDL-4bit-NanoProcessor-FPGA.git
cd VHDL-4bit-NanoProcessor-FPGA

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1. Open Vivado and create a new project.
2. Add sources from Nanoprocessor/ (original) or Nanoprocessor-Extended/ (extended).
3. Set the target device to Basys 3 (xc7a35tcpg236-1).
4. Run synthesis, implementation, and generate the bitstream.
5. Program the FPGA with the .bit file.