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ArmPkg/Drivers/ArmGicDxe: Add ESPI support for GICv3 #11032

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@NicholasGraves NicholasGraves commented May 2, 2025

  • Add ESPI configuration to GICv3.
  • Remove mNumGicInterrupts and replace with GicIsValidSource(), GicGetGreatestIntid() APIs. mNumGicInterrupts is still used internally in GICv2.
  • Tested on qemu with the BSA test suite.

Description

Adds ESPI support to GICv3
#10869

  • Breaking change?
    • Breaking change - Does this PR cause a break in build or boot behavior?
    • Examples: Does it add a new library class or move a module to a different repo.
  • Impacts security?
    • Security - Does this PR have a direct security impact?
    • Examples: Crypto algorithm change or buffer overflow fix.
  • Includes tests?
    • Tests - Does this PR include any explicit test code?
    • Examples: Unit tests or integration tests.

How This Was Tested

Tested on qemu with ESPI support via the BSA ACS test suite.

Integration Instructions

N/A

@NicholasGraves NicholasGraves changed the title #10869 ArmPkg/Drivers/ArmGicDxe: Add ESPI support for GICv3 ArmPkg/Drivers/ArmGicDxe: Add ESPI support for GICv3 May 5, 2025
@NicholasGraves NicholasGraves force-pushed the espi-upstream branch 2 times, most recently from a450368 to a916600 Compare May 7, 2025 00:35
@leiflindholm
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Thanks for this, it's definitely a gap that needs closing.

I'll do a more detailed review later today, but two high-level comments:

  • ESPI is a heavily clashing acronym. This is probably why the GIC ARM consistently refers to it as Extended SPI. I think that would be helpful to do here too.
  • Is there any way to break this up into a few more commits? Bullet points in commit messages frequently indicate there is.

This commit enables extended SPI support for GicV3. GicV3 must decide,
based on the source intid, whether to access the SPI-range registers,
PPI-range registers in the redistributor, or the extended SPI-range
registers.

The protocol interfaces must also support registering an interrupt
handler with an extended SPI intid. To save ~24KB of memory, handler
allocation and access is delegated to GicV2 and GicV3. GicV2 retains the
existing handler mapping scheme using intids literally. GicV3 remaps
extended SPI intids to be immediately after the highest SPI intids.

Tested on qemu with the BSA test suite.

Signed-off-by: Nick Graves <[email protected]>
@NicholasGraves
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Thanks for this, it's definitely a gap that needs closing.

I'll do a more detailed review later today, but two high-level comments:

  • ESPI is a heavily clashing acronym. This is probably why the GIC ARM consistently refers to it as Extended SPI. I think that would be helpful to do here too.
  • Is there any way to break this up into a few more commits? Bullet points in commit messages frequently indicate there is.

Changed ESPI -> ExtSpi in code and extended SPI in comments.

I don't think it's possible to easily break this up into atomic changes that are all functional.

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2 participants