Validate incompatible cache_modifier/eviction_policy combinations in NVIDIA backend

[swjng]

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Why

When tl.load/tl.store is called with a PTX-illegal combination of cache_modifier and eviction_policy, Triton emits PTX that ptxas then rejects with an opaque assembler error:

ptxas error: Modifier '.evict_first' cannot be combined with modifier '.cs'

Users see a low-level message with no indication of which Python arguments caused it. The PTX ISA forbids combining certain cache modifiers with L1 eviction hints:

• .cs (cache streaming) bypasses L1; L1 eviction hints are undefined.
• .ca (cache all, load) overrides L1 eviction policy; hints conflict.
• .cg (cache global) bypasses L1; evict_first is invalid.

What the fix does

Validate the combinations at PTX lowering time in third_party/nvidia/lib/TritonNVIDIAGPUToLLVM/LoadStoreOpToLLVM.cpp (LoadOpConversion::matchAndRewrite and StoreOpConversion::matchAndRewrite). On an illegal combination, emit a clear op.emitOpError before generating PTX.

The check lives in the NVIDIA backend, not the backend-agnostic semantic.py, so the Triton frontend remains neutral to PTX ISA constraints.

Combinations covered:

op	cache_modifier	eviction_policy
store	.cs	evict_first, evict_last
store	.cg	evict_first
load	.ca	evict_first, evict_last
load	.cg	evict_first

Example error after this fix:

error: cache_modifier '.cs' is incompatible with eviction_policy
'evict_first'/'evict_last': .cs bypasses L1 cache

Test plan

Added lit test cases to test/Conversion/tritongpu_to_llvm.mlir alongside the existing store_with_cache_attr / load_with_l2_cache_hint / store_with_l2_cache_hint tests. --verify-diagnostics was added to the existing RUN line so each illegal combination is checked via expected-error. Existing valid-path tests continue to pass unchanged.

[Jokeren]

load is generic across different backends and not always lowered to PTX

[swjng]

Thanks for the feedback. Moved the validation out of semantic.py into LoadStoreOpToLLVM.cpp in the NVIDIA PTX codegen pass, right before the PTX instruction builder runs. The check now lives at the correct layer — it only fires for the NVIDIA backend and is expressed as op.emitOpError() returning failure(). Updated the tests to expect triton.CompilationError instead of ValueError.

[Jokeren]

1. In this case it should be an MLIR test
2. Please update your PR description as well

[ThomasRaoux]

In triton we should not error in the compiler from a valid kernel

[swjng]

@Jokeren — moved the test to test/Conversion/tritongpu_to_llvm.mlir as a lit test with expected-error, and updated the title/description.

@ThomasRaoux — on reflection the kernel is valid at the Triton level (both .cs and evict_first are documented tl.store arguments); the conflict is purely a PTX ISA restriction, which isn't something Triton can or should fix.

One alternative before closing: the NVIDIA backend could silently drop one of the two hints (e.g. keep .cs, drop the eviction hint) and log a warning, so the kernel still compiles. Do you see value in that, or should I just close this and let ptxas surface the error?