fix: derive KiCad project design rules from exported traces and vias#208
fix: derive KiCad project design rules from exported traces and vias#208techmannih2 wants to merge 1 commit intotscircuit:mainfrom
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| return [...clearances].sort((a, b) => a - b)[0] ?? 0 |
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collectTraceClearance() returns 0 whenever the circuit has no pcb_group.autorouter_configuration.trace_clearance, and that zero is propagated into the Default netclass and board rule clearances. For common inputs that have routed traces but no pcb_group, this effectively disables spacing checks in the exported project, so KiCad can permit zero-clearance routing/zone behavior; use a nonzero fallback when no explicit clearance is available.
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| const DEFAULT_VIA_DIAMETER = 0.6 | ||
| const DEFAULT_VIA_DRILL = 0.3 |
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The fallback defaults here (0.6 / 0.3) diverge from the PCB exporter fallback (0.8 / 0.4 in lib/pcb/stages/AddViasStage.ts:191-192). When via sizes are absent in Circuit JSON and cannot be inferred, .kicad_pro and .kicad_pcb end up with different default via geometry, so continuing routing in KiCad can create vias that do not match the sizes used in the exported board.
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@techmannih i think the motivation of this change is exposing the DRC setting config from the converter.
in my opinion we are forcing the kicad to valid our invalid design.
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