test(repro02,repro03): assert exact board solid count to guard hole-cut and wrapper-exclusion paths

[colorbank]

Summary

Tightens STEP regression coverage for two board-only fixtures that were previously guarded only by a loose meshes.length > 0 OCCT import check.

repro02 — rotated-pill hole board

Adds an exact solidCount assertion after the existing MANIFOLD_SOLID_BREP presence check:

const solidCount = (stepText.match(/MANIFOLD_SOLID_BREP/g) || []).length
expect(solidCount).toBe(1)

Why 1? repro02.json contains source_components (MP1-4, Xpattern1-4) but no pcb_component entries. The STEP converter only generates component boxes for cad_component records. Without those, the board itself is the only solid. A regression that:

• fragments the board during rotated-pill hole subtraction, or
• adds spurious boxes for source-only components

…would cause solidCount > 1 and fail this guard.

repro03 — hole-wrapper component exclusion

Adds two new assertions:

1. expect(stepText).toContain("MANIFOLD_SOLID_BREP") — basic presence check (was missing)
2. solidCount = 1 guard — hole-wrapper pcb_components must never receive fallback boxes

Why 1? All pcb_component entries in repro03.json are subcircuit hole-wrapper containers (obstructs_within_bounds). Restoring the erroneous fallback that generates boxes for these wrappers would push solidCount above 1 and fail the test — exactly the regression repro03 was designed to catch.

Non-overlap with existing open PRs

PR	Files changed
#94, #97	basics04, repro01
#96	basics06, kicad-step
#95	repro04 + production fallback code
#98	Production code (pcb_silkscreen_rect, pcb_smtpad)
This PR	repro02, repro03 — untouched by all above

No conflicts, purely additive test assertions on two fixtures not covered by any open PR.

/claim #6

[vercel]

@colorbank is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.

[colorbank]

Quick unblock request: the code CI checks are green, but the remaining failing status is Vercel authorization.

Current status:

• Format Check/format-check, Bun Test/test, and Type Check/type-check are all passing.
• The only failing status is Vercel with Authorization required to deploy.
• No code/test failure is showing on the PR checks.

Could a tscircuit team member please authorize the Vercel deployment so the final status can proceed? Thank you!

[colorbank]

Hi maintainers — quick follow-up on this claim.

My Algora claim for this PR is still showing Pending: https://algora.io/claims/E88WdA3bZxZQuaT8
My payout account is already active, so I believe the remaining blocker is maintainer-side review/release plus the Vercel authorization on this PR.

Current status from the PR:

• format-check ✅
• test ✅
• type-check ✅
• Vercel is still blocked on authorization

If this looks good, could someone please authorize the Vercel deployment and help review/release the associated bounty claim? Thank you!