tum-ei-eda · PhilippvK · Jun 19, 2026 · Jun 19, 2026
diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,8 +1,9 @@
-# Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+# Generated on Fri, 19 Jun 2026 11:48:00 +0000.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
 PROJECT(RV32IMACFD)
+FIND_PACKAGE(ETISS)
 
 SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
 SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
@@ -28,25 +29,27 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_tum_semihostingInstr.cpp
 )
 
-add_custom_command(
-	TARGET ${PROJECT_NAME} POST_BUILD
-	COMMAND ${CMAKE_COMMAND} -E copy
-		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
-		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
-)
+IF(ETISS_BINARY_DIR)
+	ADD_CUSTOM_COMMAND(
+		TARGET ${PROJECT_NAME} POST_BUILD
+		COMMAND ${CMAKE_COMMAND} -E copy
+			"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+			"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+	)
+ENDIF()
 INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
 
 # handle gdbserver xml files
-if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/xml")
-	add_custom_target(copy_${PROJECT_NAME}_xml ALL
+IF(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/xml")
+	ADD_CUSTOM_TARGET(copy_${PROJECT_NAME}_xml ALL
 		COMMAND ${CMAKE_COMMAND} -E make_directory
 			"${CMAKE_CURRENT_LIST_DIR}/xml"
 		COMMAND ${CMAKE_COMMAND} -E copy_directory
 			"${CMAKE_CURRENT_LIST_DIR}/xml"
 			"${ETISS_BINARY_DIR}/xml/${PROJECT_NAME}"
 	)
-	add_dependencies(${PROJECT_NAME} copy_${PROJECT_NAME}_xml)
-	install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/xml/ DESTINATION xml/${PROJECT_NAME})
-endif()
+	ADD_DEPENDENCIES(${PROJECT_NAME} copy_${PROJECT_NAME}_xml)
+	INSTALL(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/xml/ DESTINATION xml/${PROJECT_NAME})
+ENDIF()
 
 ETISSPluginArch(${PROJECT_NAME})
diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,12 +1,11 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
 
 #ifndef ETISS_RV32IMACFDArch_RV32IMACFD_H_
 #define ETISS_RV32IMACFDArch_RV32IMACFD_H_
-#include <stdio.h>
 #include "etiss/jit/CPU.h"
 
 #ifdef __cplusplus

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the architecture specific implementation for the RV32IMACFD
  * core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the function implementations for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the function prototypes for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *
@@ -72,7 +72,7 @@
        return 33;
    }

    etiss::uint64 getInstructionPointer(ETISS_CPU *cpu) { return cpu->instructionPointer; }

    bool isLittleEndian()
    {

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:15 +0000.
+ * Generated on Fri, 19 Jun 2026 11:48:00 +0000.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt
@@ -1,8 +1,9 @@
-# Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+# Generated on Fri, 19 Jun 2026 11:47:54 +0000.
 #
 # This file contains the CMake build info for the RV64IMACFD core architecture.
 
 PROJECT(RV64IMACFD)
+FIND_PACKAGE(ETISS)
 
 SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
 SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
@@ -35,25 +36,27 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV64IMACFD_tum_semihostingInstr.cpp
 )
 
-add_custom_command(
-	TARGET ${PROJECT_NAME} POST_BUILD
-	COMMAND ${CMAKE_COMMAND} -E copy
-		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
-		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
-)
+IF(ETISS_BINARY_DIR)
+	ADD_CUSTOM_COMMAND(
+		TARGET ${PROJECT_NAME} POST_BUILD
+		COMMAND ${CMAKE_COMMAND} -E copy
+			"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+			"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+	)
+ENDIF()
 INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
 
 # handle gdbserver xml files
-if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/xml")
-	add_custom_target(copy_${PROJECT_NAME}_xml ALL
+IF(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/xml")
+	ADD_CUSTOM_TARGET(copy_${PROJECT_NAME}_xml ALL
 		COMMAND ${CMAKE_COMMAND} -E make_directory
 			"${CMAKE_CURRENT_LIST_DIR}/xml"
 		COMMAND ${CMAKE_COMMAND} -E copy_directory
 			"${CMAKE_CURRENT_LIST_DIR}/xml"
 			"${ETISS_BINARY_DIR}/xml/${PROJECT_NAME}"
 	)
-	add_dependencies(${PROJECT_NAME} copy_${PROJECT_NAME}_xml)
-	install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/xml/ DESTINATION xml/${PROJECT_NAME})
-endif()
+	ADD_DEPENDENCIES(${PROJECT_NAME} copy_${PROJECT_NAME}_xml)
+	INSTALL(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/xml/ DESTINATION xml/${PROJECT_NAME})
+ENDIF()
 
 ETISSPluginArch(${PROJECT_NAME})
diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h
@@ -1,12 +1,11 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the registers for the RV64IMACFD core architecture.
  */
 
 #ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_
 #define ETISS_RV64IMACFDArch_RV64IMACFD_H_
-#include <stdio.h>
 #include "etiss/jit/CPU.h"
 
 #ifdef __cplusplus

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the architecture class for the RV64IMACFD core architecture.
  */

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the library interface for the RV64IMACFD core architecture.
  */

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the architecture specific implementation for the RV64IMACFD
  * core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the architecture specific header for the RV64IMACFD
  * core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the function implementations for the RV64IMACFD core architecture.
  */

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the function prototypes for the RV64IMACFD core architecture.
  */

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the GDBCore adapter for the RV64IMACFD core architecture.
  *
@@ -72,7 +72,7 @@
        return 33;
    }

    etiss::uint64 getInstructionPointer(ETISS_CPU *cpu) { return cpu->instructionPointer; }

    bool isLittleEndian()
    {

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV64IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV64IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV64IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV64IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV64IMACFD core architecture.

diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp
@@ -1,6 +1,6 @@
 // clang-format off
 /**
- * Generated on Fri, 19 Jun 2026 08:11:16 +0000.
+ * Generated on Fri, 19 Jun 2026 11:47:54 +0000.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV64IMACFD core architecture.