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jerryz123jerryz123
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Improve naming of Serial-TL PhyParams
1 parent ea21d8f commit 07e1ecc

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12 files changed

+40
-40
lines changed

12 files changed

+40
-40
lines changed

‎fpga/src/main/scala/arty100t/HarnessBinders.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,8 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
6262
harnessIO match {
6363
case io: DecoupledPhitIO => {
6464
val clkIO = io match {
65-
case io: InternalSyncPhitIO => IOPin(io.clock_out)
66-
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
65+
case io: HasClockOut => IOPin(io.clock_out)
66+
case io: HasClockIn => IOPin(io.clock_in)
6767
}
6868
val packagePinsWithPackageIOs = Seq(
6969
("G13", clkIO),
@@ -87,10 +87,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
8787

8888
// Don't add IOB to the clock, if its an input
8989
io match {
90-
case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
90+
case io: DecoupledInternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
9191
artyTh.xdc.addIOB(io)
9292
}}
93-
case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
93+
case io: DecoupledExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
9494
artyTh.xdc.addIOB(io)
9595
}}
9696
}

‎fpga/src/main/scala/datastorm/HarnessBinders.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ class WithDatastormSerialTLToFMC extends HarnessBinder({
3838
harnessIO match {
3939
case io: DecoupledPhitIO => {
4040
val clkIO = io match {
41-
case io: InternalSyncPhitIO => IOPin(io.clock_out)
42-
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
41+
case io: HasClockOut => IOPin(io.clock_out)
42+
case io: HasClockIn => IOPin(io.clock_in)
4343
}
4444
val packagePinsWithPackageIOs = Seq(
4545
("PIN_C13", clkIO),

‎fpga/src/main/scala/nexysvideo/HarnessBinders.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,8 @@ class WithNexysVideoSerialTLToGPIO extends HarnessBinder({
5757
harnessIO match {
5858
case io: DecoupledPhitIO => {
5959
val clkIO = io match {
60-
case io: InternalSyncPhitIO => IOPin(io.clock_out)
61-
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
60+
case io: HasClockOut => IOPin(io.clock_out)
61+
case io: HasClockIn => IOPin(io.clock_in)
6262
}
6363
val packagePinsWithPackageIOs = Seq(
6464
("AB22", clkIO),
@@ -82,10 +82,10 @@ class WithNexysVideoSerialTLToGPIO extends HarnessBinder({
8282

8383
// Don't add IOB to the clock, if its an input
8484
io match {
85-
case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
85+
case io: DecoupledInternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
8686
nexysTh.xdc.addIOB(io)
8787
}}
88-
case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
88+
case io: DecoupledExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
8989
nexysTh.xdc.addIOB(io)
9090
}}
9191
}

‎generators/chipyard/src/main/scala/config/AbstractConfig.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ class AbstractConfig extends Config(
7171
new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
7272
testchipip.serdes.SerialTLParams(
7373
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
74-
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
74+
phyParams = testchipip.serdes.DecoupledExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
7575
)
7676
)) ++
7777
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */

‎generators/chipyard/src/main/scala/config/ChipConfigs.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
3131
isMemoryDevice = true
3232
)),
3333
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip
34-
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock
34+
phyParams = testchipip.serdes.DecoupledExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock
3535
))) ++
3636

3737
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
@@ -78,7 +78,7 @@ class ChipBringupHostConfig extends Config(
7878
))
7979
)),
8080
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
81-
phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
81+
phyParams = testchipip.serdes.DecoupledInternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
8282
))) ++
8383

8484
//============================

‎generators/chipyard/src/main/scala/config/ChipletConfigs.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config(
1616
new testchipip.serdes.WithSerialTL(Seq(
1717
testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
1818
client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
19-
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
19+
phyParams = testchipip.serdes.DecoupledExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
2020
),
2121
testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
2222
client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
@@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config(
2727
)),
2828
slaveWhere = OBUS
2929
)),
30-
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
30+
phyParams = testchipip.serdes.CreditedSourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
3131
))
3232
) ++
3333
new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory
@@ -51,7 +51,7 @@ class RocketCoreChipletConfig extends Config(
5151
new testchipip.serdes.WithSerialTL(Seq(
5252
testchipip.serdes.SerialTLParams(
5353
client = Some(testchipip.serdes.SerialTLClientParams()),
54-
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
54+
phyParams = testchipip.serdes.DecoupledExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
5555
),
5656
testchipip.serdes.SerialTLParams(
5757
manager = Some(testchipip.serdes.SerialTLManagerParams(
@@ -62,7 +62,7 @@ class RocketCoreChipletConfig extends Config(
6262
slaveWhere = OBUS,
6363
isMemoryDevice = true
6464
)),
65-
phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
65+
phyParams = testchipip.serdes.CreditedSourceSyncSerialPhyParams()
6666
)
6767
)) ++
6868
new testchipip.soc.WithOffchipBusClient(SBUS) ++
@@ -79,7 +79,7 @@ class LLCChipletConfig extends Config(
7979
new chipyard.harness.WithSerialTLTiedOff ++
8080
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
8181
client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
82-
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
82+
phyParams = testchipip.serdes.CreditedSourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
8383
))) ++
8484
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
8585
new chipyard.NoCoresConfig

‎generators/chipyard/src/main/scala/example/FlatTestHarness.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,12 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
4747

4848
// Figure out which clock drives the harness TLSerdes, based on the port type
4949
val serial_ram_clock = dut.serial_tl_pad match {
50-
case io: InternalSyncPhitIO => io.clock_out
51-
case io: ExternalSyncPhitIO => clock
50+
case io: HasClockOut => io.clock_out
51+
case io: HasClockIn => clock
5252
}
5353
dut.serial_tl_pad match {
54-
case io: ExternalSyncPhitIO => io.clock_in := clock
55-
case io: InternalSyncPhitIO =>
54+
case io: HasClockIn => io.clock_in := clock
55+
case io: HasClockOut =>
5656
}
5757

5858
dut.serial_tl_pad match {

‎generators/chipyard/src/main/scala/harness/HarnessBinders.scala‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -224,16 +224,16 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
224224
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
225225
port.io match {
226226
case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
227-
case io: SourceSyncPhitIO => {
227+
case io: CreditedSourceSyncPhitIO => {
228228
io.clock_in := false.B.asClock
229229
io.reset_in := false.B.asAsyncReset
230230
io.in := DontCare
231231
}
232232
}
233233
port.io match {
234-
case io: InternalSyncPhitIO =>
235-
case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
236-
case io: SourceSyncPhitIO =>
234+
case io: HasClockOut =>
235+
case io: HasClockIn => io.clock_in := false.B.asClock
236+
case io: CreditedSourceSyncPhitIO =>
237237
case _ =>
238238
}
239239
}
@@ -242,18 +242,18 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
242242
class WithSimTSIOverSerialTL extends HarnessBinder({
243243
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
244244
port.io match {
245-
case io: InternalSyncPhitIO =>
246-
case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
247-
case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
245+
case io: HasClockOut =>
246+
case io: HasClockIn => io.clock_in := th.harnessBinderClock
247+
case io: CreditedSourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
248248
}
249249

250250
port.io match {
251251
case io: DecoupledPhitIO => {
252252
// If the port is locally synchronous (provides a clock), drive everything with that clock
253253
// Else, drive everything with the harnes clock
254254
val clock = port.io match {
255-
case io: InternalSyncPhitIO => io.clock_out
256-
case io: ExternalSyncPhitIO => th.harnessBinderClock
255+
case io: HasClockOut => io.clock_out
256+
case io: HasClockIn => th.harnessBinderClock
257257
}
258258
withClock(clock) {
259259
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)

‎generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,12 +58,12 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
5858
(p0: SerialTLPort) => p0.portId == chip0portId,
5959
(p1: SerialTLPort) => p1.portId == chip1portId,
6060
(th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
61-
def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = {
61+
def connectDecoupledSyncPhitIO(clkSource: DecoupledInternalSyncPhitIO, clkSink: DecoupledExternalSyncPhitIO) = {
6262
clkSink.clock_in := clkSource.clock_out
6363
clkSink.in <> clkSource.out
6464
clkSource.in <> clkSink.out
6565
}
66-
def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = {
66+
def connectSourceSyncPhitIO(a: CreditedSourceSyncPhitIO, b: CreditedSourceSyncPhitIO) = {
6767
a.clock_in := b.clock_out
6868
b.clock_in := a.clock_out
6969
a.reset_in := b.reset_out
@@ -72,9 +72,9 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
7272
b.in := a.out
7373
}
7474
(p0.io, p1.io) match {
75-
case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
76-
case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
77-
case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1)
75+
case (io0: DecoupledInternalSyncPhitIO, io1: DecoupledExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
76+
case (io0: DecoupledExternalSyncPhitIO, io1: DecoupledInternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
77+
case (io0: CreditedSourceSyncPhitIO , io1: CreditedSourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1)
7878
}
7979
}
8080
)

‎generators/firechip/chip/src/main/scala/BridgeBinders.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ import org.chipsalliance.cde.config.{Config}
88
import freechips.rocketchip.diplomacy.{LazyModule}
99
import freechips.rocketchip.subsystem._
1010
import sifive.blocks.devices.uart._
11-
import testchipip.serdes.{ExternalSyncPhitIO}
11+
import testchipip.serdes.{DecoupledExternalSyncPhitIO}
1212
import testchipip.tsi.{SerialRAM}
1313

1414
import chipyard.iocell._
@@ -59,7 +59,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
5959
class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
6060
case (th: FireSim, port: SerialTLPort, chipId: Int) => {
6161
port.io match {
62-
case io: ExternalSyncPhitIO => {
62+
case io: DecoupledExternalSyncPhitIO => {
6363
io.clock_in := th.harnessBinderClock
6464
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
6565
ram.io.ser.in <> io.out

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