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Copy file name to clipboardExpand all lines: docs/Chipyard-Basics/Configs-Parameters-Mixins.rst
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@@ -123,3 +123,11 @@ Another description of traits/mixins and config fragments is given in :ref:`Cust
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Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY.
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.. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins).
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Optional Generator Injectors
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----------------------------
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Some generic Chipyard config fragments (for example, trace toggles and tile prefetch settings) are designed to affect optional generators without hard dependencies. Chipyard discovers generator-provided injectors at elaboration time and applies them, allowing fragments like ``WithTraceIO`` and ``WithTilePrefetchers`` to work across different tiles.
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- Generators that want to participate implement ``chipyard.config.TilePluginProvider`` under their ``generators/<name>/chipyard`` sources. Chipyard discovers implementations via classpath scanning and applies the provided injectors.
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- This keeps the core fragments generic, while enabling per-generator behavior (e.g., mapping a prefetch intent to the correct port parameters for that tile).
Copy file name to clipboardExpand all lines: docs/Chipyard-Basics/Initial-Repo-Setup.rst
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@@ -97,6 +97,8 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
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.. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
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.. Note for power users: Chipyard includes internal scripts that can selectively initialize generator submodules. The default ``./build-setup.sh`` initializes all standard generator submodules and is the recommended path.
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.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
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By running the following command you should see an environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.
Copy file name to clipboardExpand all lines: docs/Generators/CVA6.rst
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@@ -2,13 +2,19 @@ CVA6 Core
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====================================
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`CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
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The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
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The `CVA6 core` is wrapped in a `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
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The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
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.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
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While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
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Configuration classes and Chipyard glue for CVA6 live under ``generators/cva6/chipyard`` and are compiled directly from the CVA6 repository sources. After running the standard setup (``./build-setup.sh``), you can build a CVA6 config like ``CVA6Config`` with the normal flow:
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::
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cd sims/vcs && make CONFIG=CVA6Config
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.. Warning:: This target does not support Verilator simulation at this time. Please use VCS.
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For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.
Copy file name to clipboardExpand all lines: docs/Generators/Ibex.rst
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.. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
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While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
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While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
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For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
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Configuration classes and Chipyard glue for Ibex live under ``generators/ibex/chipyard`` and are compiled directly from the Ibex repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
For more information, please refer to the `GitHub repository <https://github.com/ucb-bar/riscv-sodor>`__.
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Configuration classes and Chipyard glue for Sodor live under ``generators/riscv-sodor/chipyard`` and are compiled directly from the Sodor repository sources. After running the standard setup (``./build-setup.sh``), build a config (e.g., 3-stage) with:
Copy file name to clipboardExpand all lines: docs/Generators/VexiiRiscv.rst
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The example VexiiRiscv config is ``VexiiRiscvConfig``.
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When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before integrating it as a Chisel blackbox.
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Configuration classes and Chipyard glue for VexiiRiscv live under ``generators/vexiiriscv/chipyard`` and are compiled directly from the VexiiRiscv repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
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