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3 changes: 2 additions & 1 deletion generators/firechip/chip/src/main/scala/FireSim.scala
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
// TODO: currently, fpu mem. model optimizations are broken with model multi-threading so disable for now
//r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
}
case b: BoomTile => {
val core = b.module.core
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