Bump toolchains/riscv-tools/riscv-isa-sim from 7812eab to b81b5a0
#2166
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `7812eab` to `b81b5a0`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@7812eab...b81b5a0) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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Jan 10, 2025
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This was referenced Jun 17, 2025
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Bumps toolchains/riscv-tools/riscv-isa-sim from
7812eabtob81b5a0.Commits
b81b5a0Merge pull request #1864 from riscv-software-src/ext_csr_reset4cf4915Merge pull request #1881 from riscv-software-src/spike-dasm-strict8ad998fAdd --strict command-line arg to spike-dasm1e589aaSupport strict disassembly in disassembler_tdc09460Merge pull request #1880 from riscv-software-src/fix-xdebugver0fea35dSet dcsr.xdebugver to 4, as it ought to bea2dcf1fMerge pull request #1871 from XYenChi/patch-1422c711Fix comment op namefe49242Merge pull request #1870 from riscv-software-src/ci-macos-13df2b69bMerge pull request #1866 from chihminchao/prioritize-misaligned-superpageDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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