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ADD: branch predictor mode support for tacit #2234

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fe9208e
ADD: branch predictor mode for tacit
iansseijelly Apr 14, 2025
94152b4
BUMP: all submodules
iansseijelly Apr 15, 2025
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2 changes: 1 addition & 1 deletion build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -265,7 +265,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
.settings(commonSettings)

lazy val tacit = (project in file("generators/tacit"))
.dependsOn(rocketchip, shuttle)
.dependsOn(rocketchip, shuttle, testchipip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/DigitalTop.scala
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Expand Up @@ -14,7 +14,6 @@ import freechips.rocketchip.devices.tilelink._

// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with tacit.CanHaveTraceSinkDMA
with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
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13 changes: 9 additions & 4 deletions generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,9 @@ import vexiiriscv.{VexiiRiscvTileAttachParams}
import testchipip.cosim.{TracePortKey, TracePortParams}
import barf.{TilePrefetchingMasterPortParams}
import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
import tacit.{TacitEncoder}
import tacit.{TacitEncoder, TacitBPParams}
import shuttle.common.{ShuttleTileAttachParams}

class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
Expand Down Expand Up @@ -78,8 +79,9 @@ class WithTacitEncoder extends Config((site, here, up) => {
xlen = tp.tileParams.core.xLen,
iaddrWidth = tp.tileParams.core.xLen
),
bufferDepth = 16,
coreStages = 5)(p)),
bufferDepth = 16,
coreStages = 5,
bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
useArbiterMonitor = false
)),
core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
Expand All @@ -90,7 +92,10 @@ class WithTacitEncoder extends Config((site, here, up) => {
nGroups = tp.tileParams.core.retireWidth,
xlen = tp.tileParams.core.xLen,
iaddrWidth = tp.tileParams.core.xLen
), bufferDepth = 16, coreStages = 7)(p)),
),
bufferDepth = 16,
coreStages = 7,
bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
useArbiterMonitor = false
)),
core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
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2 changes: 1 addition & 1 deletion generators/rocket-chip
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Submodule rocket-chip updated 2 files
+2 −2 src/main/scala/amba/axi4/SRAM.scala
+7 −7 src/main/scala/trace/TraceEncoderController.scala
2 changes: 1 addition & 1 deletion generators/tacit
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Submodule tacit updated 4 files
+41 −0 src/main/scala/DSCBranchPredictor.scala
+107 −25 src/main/scala/TacitEncoder.scala
+18 −2 src/main/scala/TraceSinkAlways.scala
+12 −9 src/main/scala/TraceSinkDMA.scala
2 changes: 1 addition & 1 deletion software/baremetal-ide
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Submodule baremetal-ide updated 8 files
+0 −16 driver/rocket-chip/l_trace_encoder/l_trace_encoder.c
+25 −6 driver/rocket-chip/l_trace_encoder/l_trace_encoder.h
+1 −1 examples/embench/CMakeLists.txt
+1 −1 examples/embench/common/inc/trigger.h
+501 −0 examples/embench/huffbench/libhuffbench.c
+1 −0 examples/pmu-tests/CMakeLists.txt
+1 −1 examples/pmu-tests/src/ltrace-dma-test.c
+12 −0 examples/pmu-tests/src/trace-hello.c
2 changes: 1 addition & 1 deletion software/tacit_decoder
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Submodule tacit_decoder updated 21 files
+151 −173 Cargo.lock
+2 −4 Cargo.toml
+0 −9 crates/useit_decoder/Cargo.toml
+0 −72 crates/useit_decoder/src/main.rs
+12 −0 scripts/filter_bp.py
+11 −3 scripts/find_divergence_spike.py
+1 −1 scripts/find_divergence_verilator.py
+14 −11 src/backend/event.rs
+0 −41 src/backend/json_receiver.rs
+15 −41 src/backend/stack_unwinder.rs
+83 −0 src/backend/stats_receiver.rs
+6 −5 src/backend/txt_receiver.rs
+94 −0 src/backend/vbb_receiver.rs
+54 −35 src/backend/vpp_receiver.rs
+79 −0 src/frontend/bp_double_saturating_counter.rs
+19 −0 src/frontend/br_mode.rs
+22 −0 src/frontend/c_header.rs
+43 −0 src/frontend/f_header.rs
+24 −90 src/frontend/packet.rs
+22 −0 src/frontend/trap_type.rs
+155 −84 src/main.rs
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