Modularize out most submodules

.github/workflows/chipyard-run-tests.yml

@@ -150,6 +150,7 @@ jobs:
       - name: Check that documentation builds with no warnings/errors
         run: |
           conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)
+          scripts/init-submodules-no-riscv-tools.sh --full
           make -C docs html
       - name: Show error log from sphinx if failed
         if: ${{ failure() }}

build.sbt

@@ -148,7 +148,7 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
 // -- Chipyard-managed External Projects --
 
-lazy val testchipip = (project in file("generators/testchipip"))
+lazy val testchipip = withInitCheck((project in file("generators/testchipip")), "testchipip")
   .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -160,9 +160,9 @@ lazy val chipyard = {
     .dependsOn(
       testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
       dsptools, rocket_dsp_utils,
-      radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+      icenet, tracegen,
       constellation, barf, shuttle, rerocc,
-      firrtl2_bridge, vexiiriscv, tacit
+      firrtl2_bridge
     )
     .settings(libraryDependencies ++= rocketLibDeps.value)
     .settings(
@@ -175,11 +175,21 @@ lazy val chipyard = {
 
   // Optional modules discovered via initialized submodules (no env or manifest)
   val optionalModules: Seq[(String, ProjectReference)] = Seq(
+    // Generators with Chipyard-facing glue compiled from their repos
+    "cva6" -> cva6,
+    "ibex" -> ibex,
+    "vexiiriscv" -> vexiiriscv,
+    "riscv-sodor" -> sodor,
     "ara" -> ara,
     "saturn" -> saturn,
+    "tacit" -> tacit,
+    "gemmini" -> gemmini,
+    "nvdla" -> nvdla,
+    "radiance" -> radiance,
     "caliptra-aes-acc" -> caliptra_aes,
     "compress-acc" -> compressacc,
-    "mempress" -> mempress
+    "mempress" -> mempress,
+    "fft-generator" -> fft_generator
   )
 
   // Discover optional modules if their submodule is initialized
@@ -205,32 +215,32 @@ lazy val chipyard = {
   cy
 }
 
-lazy val compressacc = (project in file("generators/compress-acc"))
+lazy val compressacc = withInitCheck((project in file("generators/compress-acc")), "compress-acc")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val mempress = (project in file("generators/mempress"))
+lazy val mempress = withInitCheck((project in file("generators/mempress")), "mempress")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val barf = (project in file("generators/bar-fetchers"))
+lazy val barf = withInitCheck((project in file("generators/bar-fetchers")), "bar-fetchers")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val saturn = (project in file("generators/saturn"))
+lazy val saturn = withInitCheck((project in file("generators/saturn")), "saturn")
   .dependsOn(rocketchip, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val constellation = (project in file("generators/constellation"))
+lazy val constellation = withInitCheck((project in file("generators/constellation")), "constellation")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val fft_generator = (project in file("generators/fft-generator"))
+lazy val fft_generator = withInitCheck((project in file("generators/fft-generator")), "fft-generator")
   .dependsOn(rocketchip, rocket_dsp_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -240,7 +250,7 @@ lazy val tracegen = (project in file("generators/tracegen"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val icenet = (project in file("generators/icenet"))
+lazy val icenet = withInitCheck((project in file("generators/icenet")), "icenet")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -250,37 +260,57 @@ lazy val boom = freshProject("boom", file("generators/boom"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val shuttle = (project in file("generators/shuttle"))
+lazy val shuttle = withInitCheck((project in file("generators/shuttle")), "shuttle")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val cva6 = (project in file("generators/cva6"))
+// Helper: fail fast if a generator project is used without its submodule initialized.
+def withInitCheck(p: Project, genDirName: String): Project = {
+  val checkTask = Def.task {
+    val root = (ThisBuild / baseDirectory).value
+    val dir = root / s"generators/$genDirName"
+    val looksInitialized = (dir / ".git").exists
+    if (!dir.exists || !looksInitialized) {
+      sys.error(
+        s"Generator '$genDirName' is not initialized at '" + dir.getAbsolutePath +
+        "'. Run scripts/build-setup.sh or init the submodule (scripts/init-submodules-no-riscv-tools-nolog.sh).")
+    }
+  }
+  p.settings(
+    // Run the check whenever this project's code is compiled/tested/run
+    Compile / compile := (Compile / compile).dependsOn(checkTask).value,
+    Test / compile := (Test / compile).dependsOn(checkTask).value,
+    Compile / run := (Compile / run).dependsOn(checkTask).evaluated
+  )
+}
+
+lazy val cva6 = withInitCheck((project in file("generators/cva6")), "cva6")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val ara = (project in file("generators/ara"))
+lazy val ara = withInitCheck((project in file("generators/ara")), "ara")
   .dependsOn(rocketchip, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val ibex = (project in file("generators/ibex"))
+lazy val ibex = withInitCheck((project in file("generators/ibex")), "ibex")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val vexiiriscv = (project in file("generators/vexiiriscv"))
+lazy val vexiiriscv = withInitCheck((project in file("generators/vexiiriscv")), "vexiiriscv")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sodor = (project in file("generators/riscv-sodor"))
+lazy val sodor = withInitCheck((project in file("generators/riscv-sodor")), "riscv-sodor")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val radiance = (project in file("generators/radiance"))
+lazy val radiance = withInitCheck((project in file("generators/radiance")), "radiance")
   .dependsOn(rocketchip, gemmini, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(libraryDependencies ++= Seq(
@@ -291,32 +321,32 @@ lazy val radiance = (project in file("generators/radiance"))
   ))
   .settings(commonSettings)
 
-lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
+lazy val gemmini = withInitCheck(freshProject("gemmini", file("generators/gemmini")), "gemmini")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val nvdla = (project in file("generators/nvdla"))
+lazy val nvdla = withInitCheck((project in file("generators/nvdla")), "nvdla")
   .dependsOn(rocketchip, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val tacit = (project in file("generators/tacit"))
+lazy val tacit = withInitCheck((project in file("generators/tacit")), "tacit")
   .dependsOn(rocketchip, shuttle, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
+lazy val caliptra_aes = withInitCheck((project in file("generators/caliptra-aes-acc")), "caliptra-aes-acc")
   .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rerocc = (project in file("generators/rerocc"))
+lazy val rerocc = withInitCheck((project in file("generators/rerocc")), "rerocc")
   .dependsOn(rocketchip, constellation, boom, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
+lazy val rocc_acc_utils = withInitCheck((project in file("generators/rocc-acc-utils")), "rocc-acc-utils")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -354,12 +384,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
+lazy val rocketchip_blocks = withInitCheck((project in file("generators/rocket-chip-blocks")), "rocket-chip-blocks")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
+lazy val rocketchip_inclusive_cache = withInitCheck((project in file("generators/rocket-chip-inclusive-cache")), "rocket-chip-inclusive-cache")
   .settings(
     commonSettings,
     Compile / scalaSource := baseDirectory.value / "design/craft")

common.mk

@@ -68,8 +68,7 @@ HELP_COMMANDS += \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
 "   find-configs                = list Chipyard Config classes (eligible CONFIG=)" \
-"   find-config-fragments       = list all config. fragments" \
-"   check-submodule-status      = check that all submodules in generators/ have been initialized"
+"   find-config-fragments       = list all config. fragments"
 
 #########################################################################################
 # include additional subproject make fragments
@@ -78,10 +77,6 @@ HELP_COMMANDS += \
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/tools/torture.mk
 # Optional generator make fragments should not fail build if absent
--include $(base_dir)/generators/cva6/cva6.mk
--include $(base_dir)/generators/ibex/ibex.mk
--include $(base_dir)/generators/nvdla/nvdla.mk
--include $(base_dir)/generators/radiance/radiance.mk
 # Wildcard include for standardized per-generator make fragments
 -include $(wildcard $(base_dir)/generators/*/chipyard.mk)
 
@@ -100,8 +95,6 @@ endif
 # Returns a list of files in directories $1 with *any* of the file extensions in $2
 lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
 
-CHECK_SUBMODULES_COMMAND = echo "Checking required submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep '^-.*' | grep -vE "(ara|caliptra|compress|mempress|saturn)"
-
 SCALA_EXT = scala
 VLOG_EXT = sv v
 FIRESIM_SOURCE_DIRS = $(addprefix sims/firesim/,sim/firesim-lib sim/midas/targetutils) $(addprefix generators/firechip/,chip bridgeinterfaces bridgestubs) tools/firrtl2
@@ -124,7 +117,6 @@ $(build_dir):
 # compile scala jars
 #########################################################################################
 $(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
-	$(CHECK_SUBMODULES_COMMAND)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH))
 
@@ -460,14 +452,6 @@ find-configs:
 help:
 	@for line in $(HELP_LINES); do echo "$$line"; done
 
-#########################################################################################
-# Check submodule status
-#########################################################################################
-
-.PHONY: check-submodule-status
-check-submodule-status:
-	$(CHECK_SUBMODULES_COMMAND)
-
 #########################################################################################
 # Implicit rule handling
 #########################################################################################

docs/Chipyard-Basics/Configs-Parameters-Mixins.rst

@@ -123,3 +123,11 @@ Another description of traits/mixins and config fragments is given in :ref:`Cust
 Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY.
 
 .. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins).
+
+Optional Generator Injectors
+----------------------------
+
+Some generic Chipyard config fragments (for example, trace toggles and tile prefetch settings) are designed to affect optional generators without hard dependencies. Chipyard discovers generator-provided injectors at elaboration time and applies them, allowing fragments like ``WithTraceIO`` and ``WithTilePrefetchers`` to work across different tiles.
+
+- Generators that want to participate implement ``chipyard.config.TilePluginProvider`` under their ``generators/<name>/chipyard`` sources. Chipyard discovers implementations via classpath scanning and applies the provided injectors.
+- This keeps the core fragments generic, while enabling per-generator behavior (e.g., mapping a prefetch intent to the correct port parameters for that tile).

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -97,6 +97,8 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
 
 .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
 
+.. Note for power users: Chipyard includes internal scripts that can selectively initialize generator submodules. The default ``./build-setup.sh`` initializes all standard generator submodules and is the recommended path.
+
 .. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
 
 By running the following command you should see an environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.

docs/Generators/CVA6.rst

@@ -2,13 +2,19 @@ CVA6 Core
 ====================================
 
 `CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
-The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+The `CVA6 core` is wrapped in a `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
 
 .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
 
 While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
 
+Configuration classes and Chipyard glue for CVA6 live under ``generators/cva6/chipyard`` and are compiled directly from the CVA6 repository sources. After running the standard setup (``./build-setup.sh``), you can build a CVA6 config like ``CVA6Config`` with the normal flow:
+
+::
+
+  cd sims/vcs && make CONFIG=CVA6Config
+
 .. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
 
 For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.

docs/Generators/Ibex.rst

@@ -9,6 +9,12 @@ The core exposes a custom memory interface, interrupt ports, and other misc. por
 
 .. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
 
-While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
-
+While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
+
 For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
+
+Configuration classes and Chipyard glue for Ibex live under ``generators/ibex/chipyard`` and are compiled directly from the Ibex repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=IbexConfig

docs/Generators/Sodor.rst

@@ -15,3 +15,9 @@ The five available cores and their corresponding generator configuration are:
 * "bus"-based micro-coded implementation - ``SodorUCodeConfig``
 
 For more information, please refer to the `GitHub repository <https://github.com/ucb-bar/riscv-sodor>`__.
+
+Configuration classes and Chipyard glue for Sodor live under ``generators/riscv-sodor/chipyard`` and are compiled directly from the Sodor repository sources. After running the standard setup (``./build-setup.sh``), build a config (e.g., 3-stage) with:
+
+::
+
+  cd sims/vcs && make CONFIG=Sodor3StageConfig

docs/Generators/VexiiRiscv.rst

@@ -7,3 +7,8 @@ VexiiRiscv implements cache-coherent TileLink L1 data caches and is integrated a
 The example VexiiRiscv config is ``VexiiRiscvConfig``.
 When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before integrating it as a Chisel blackbox.
 
+Configuration classes and Chipyard glue for VexiiRiscv live under ``generators/vexiiriscv/chipyard`` and are compiled directly from the VexiiRiscv repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=VexiiRiscvConfig

docs/Generators/fft.rst

@@ -7,7 +7,7 @@ Configuration
 --------------------------
 The following configuration creates an 8-point FFT:
 
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+.. literalinclude:: ../../generators/fft-generator/chipyard/FFTConfigs.scala
    :language: scala
    :start-after: DOC include start: FFTRocketConfig
    :end-before: DOC include end: FFTRocketConfig