Bump toolchains/riscv-tools/riscv-isa-sim from 7812eab to 49727e8#12
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `7812eab` to `49727e8`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@7812eab...49727e8) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Superseded by #14. |
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Bumps toolchains/riscv-tools/riscv-isa-sim from
7812eabto49727e8.Commits
49727e8Merge pull request #1889 from ved-rivos/0109250bbf0d6(Guest)Page fault cause by Svnapot occur before A/D updatefa05e4eMerge pull request #1887 from fly-1011/fix-hvip-lcofi34195bbFix LCOFI bit implementation in hvip registerb81b5a0Merge pull request #1864 from riscv-software-src/ext_csr_reset4cf4915Merge pull request #1881 from riscv-software-src/spike-dasm-strict8ad998fAdd --strict command-line arg to spike-dasm1e589aaSupport strict disassembly in disassembler_tdc09460Merge pull request #1880 from riscv-software-src/fix-xdebugver0fea35dSet dcsr.xdebugver to 4, as it ought to beDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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