Bump toolchains/riscv-tools/riscv-isa-sim from 7812eab to 3f79e3b#36
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `7812eab` to `3f79e3b`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@7812eab...3f79e3b) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Superseded by #37. |
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Bumps toolchains/riscv-tools/riscv-isa-sim from
7812eabto3f79e3b.Commits
3f79e3bMerge pull request #1930 from aap-sc/aap-sc/abits_len_fixupaa074f2increase DTMCS.abits to be compliant debug specification643e6c6Merge pull request #1923 from fhunstock-semron/fesvr-non-htif-bootloader-supportb8eab30Merge pull request #1926 from riscv-software-src/fix-1925283b6afCheck for NAPOT PTE validity before raising SS-related faults79718edDon't send reset from HTIF, if no binary is given81d92f3Load symbols even when no binary is given14876b3allow to set tohost/from host via --symbol-elf9b44f4bMerge pull request #1920 from riscv-software-src/zvqdotq5ed426bAdd Zvqdotq extensionDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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