Setup qol changes

[jimfangx]

Addresses setup failing if 151 Verilog is not included -- Students are not required to include their 151 core in labs 1. This will allow setup to finish without their RTL, then corresponding instructions (ucb-eecs151tapeout/eecs151t-labs#4) in Lab 2 will tell then to enable + integrate the OFO generator into build system

Addresses ara failing during step 5 of build-setup; added - to common.mk to allow command to fail if ara.mk is not found. added backup (allowed to fail) to setup chipyard.mk instead if that is found in any generator

Related PRs / Issues: None

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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• Did you set main as the base branch?
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• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
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[lorenshung]

lgtm