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uclid-org / chiselucl Public

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Rearchitecting the tool flow (Not ready to merge)#1

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d0cd wants to merge 11 commits intomasteruclid-org/chiselucl:masterfrom

d0cd/re-archuclid-org/chiselucl:d0cd/re-archCopy head branch name to clipboard

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Rearchitecting the tool flow (Not ready to merge)#1
d0cd wants to merge 11 commits intomasterfrom
d0cd/re-arch

Commits

Commits on Mar 23, 2020

Updated scala version
d0cd
committed
Reorganized project structure
d0cd
committed
Added base for a general verification language
d0cd
committed
Created annotations for circuit analysis passes; fixed compiler errors in verification lang
d0cd
committed

Commits on Mar 24, 2020

Created CollectCircuitInfo transform
d0cd
committed
Added CollectModuleInfo transform and decoupled UCLID logic; cleaned up CollectInfo.scala
d0cd
committed
Added ExpandMemoryWires transform; minor changes to CollectModuleInfo
d0cd
committed
Split structure of ModuleInfoAnnotation; made other passes compatible with the change
d0cd
committed
Added ComputeClockDomain pass (needs reimplementation); moving to emission
d0cd
committed
Modified structure of verification stages
d0cd
committed
Added scaffolding for emitting UCLID, need to figure out the emission API in FIRRTL
d0cd
committed

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