Remove remaining global and static varaibels in the placement stage

libs/libarchfpga/src/arch_util.cpp

@@ -152,17 +152,11 @@ void free_arch(t_arch* arch) {
         return;
     }
 
-    delete[] arch->Switches;
-    arch->Switches = nullptr;
-
     free_arch_models(arch->models);
 
-    for (int i = 0; i < arch->num_directs; ++i) {
-        vtr::free(arch->Directs[i].name);
-        vtr::free(arch->Directs[i].from_pin);
-        vtr::free(arch->Directs[i].to_pin);
-    }
-    vtr::free(arch->Directs);
+    vtr::release_memory(arch->switches);
+
+    vtr::release_memory(arch->Directs);
 
     vtr::free(arch->architecture_id);
 
@@ -235,7 +229,7 @@ t_model* free_arch_model(t_model* model) {
     return next_model;
 }
 
-//Frees all the model portss in a linked list
+//Frees all the model ports in a linked list
 void free_arch_model_ports(t_model_ports* model_ports) {
     t_model_ports* model_port = model_ports;
     while (model_port) {

libs/libarchfpga/src/echo_arch.cpp

@@ -253,29 +253,29 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
     //13 is hard coded because format of %e is always 1.123456e+12
     //It always consists of 10 alphanumeric digits, a decimal
     //and a sign
-    for (i = 0; i < arch->num_switches; i++) {
-        if (arch->Switches[i].type() == SwitchType::MUX) {
-            fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->Switches[i].name.c_str());
-        } else if (arch->Switches[i].type() == SwitchType::TRISTATE) {
-            fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->Switches[i].name.c_str());
-        } else if (arch->Switches[i].type() == SwitchType::SHORT) {
-            fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->Switches[i].name.c_str());
-        } else if (arch->Switches[i].type() == SwitchType::BUFFER) {
-            fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->Switches[i].name.c_str());
+    for (i = 0; i < (int)arch->switches.size(); i++) {
+        if (arch->switches[i].type() == SwitchType::MUX) {
+            fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->switches[i].name.c_str());
+        } else if (arch->switches[i].type() == SwitchType::TRISTATE) {
+            fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->switches[i].name.c_str());
+        } else if (arch->switches[i].type() == SwitchType::SHORT) {
+            fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->switches[i].name.c_str());
+        } else if (arch->switches[i].type() == SwitchType::BUFFER) {
+            fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->switches[i].name.c_str());
         } else {
-            VTR_ASSERT(arch->Switches[i].type() == SwitchType::PASS_GATE);
-            fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->Switches[i].name.c_str());
+            VTR_ASSERT(arch->switches[i].type() == SwitchType::PASS_GATE);
+            fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->switches[i].name.c_str());
         }
-        fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->Switches[i].R,
-                arch->Switches[i].Cin, arch->Switches[i].Cout);
+        fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->switches[i].R,
+                arch->switches[i].Cin, arch->switches[i].Cout);
         fprintf(Echo, "\t\t\t\t#Tdel values %d buf_size %e mux_trans_size %e\n",
-                (int)arch->Switches[i].Tdel_map_.size(), arch->Switches[i].buf_size,
-                arch->Switches[i].mux_trans_size);
-        if (arch->Switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) {
+                (int)arch->switches[i].Tdel_map_.size(), arch->switches[i].buf_size,
+                arch->switches[i].mux_trans_size);
+        if (arch->switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) {
             fprintf(Echo, "\t\t\t\tpower_buffer_size auto\n");
         } else {
             fprintf(Echo, "\t\t\t\tpower_buffer_size %e\n",
-                    arch->Switches[i].power_buffer_size);
+                    arch->switches[i].power_buffer_size);
         }
     }
 
@@ -293,19 +293,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
         if (seg.directionality == UNI_DIRECTIONAL) {
             //wire_switch == arch_opin_switch
             fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n",
-                    arch->Switches[seg.arch_wire_switch].name.c_str());
+                    arch->switches[seg.arch_wire_switch].name.c_str());
             //if there is more than one layer available, print the segment switch name that is used for connection between two dice
             for (const auto& layout : arch->grid_layouts) {
                 int num_layers = (int)layout.layers.size();
                 if (num_layers > 1) {
                     fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
-                            arch->Switches[seg.arch_opin_between_dice_switch].name.c_str());
+                            arch->switches[seg.arch_opin_between_dice_switch].name.c_str());
                 }
             }
         } else { //Should be bidir
             fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",
-                    arch->Switches[seg.arch_wire_switch].name.c_str(),
-                    arch->Switches[seg.arch_opin_switch].name.c_str());
+                    arch->switches[seg.arch_wire_switch].name.c_str(),
+                    arch->switches[seg.arch_opin_switch].name.c_str());
         }
 
         fprintf(Echo, "\t\t\t\tcb ");
@@ -332,10 +332,10 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
     //Direct List
     fprintf(Echo, "*************************************************\n");
     fprintf(Echo, "Direct List:\n");
-    for (i = 0; i < arch->num_directs; i++) {
+    for (i = 0; i < (int)arch->Directs.size(); i++) {
         fprintf(Echo, "\tDirect[%d]: name %s from_pin %s to_pin %s\n", i + 1,
-                arch->Directs[i].name, arch->Directs[i].from_pin,
-                arch->Directs[i].to_pin);
+                arch->Directs[i].name.c_str(), arch->Directs[i].from_pin.c_str(),
+                arch->Directs[i].to_pin.c_str());
         fprintf(Echo, "\t\t\t\t x_offset %d y_offset %d z_offset %d\n",
                 arch->Directs[i].x_offset, arch->Directs[i].y_offset,
                 arch->Directs[i].sub_tile_offset);
@@ -347,7 +347,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
         fprintf(Echo, "*************************************************\n");
         fprintf(Echo, "NoC Router Connection List:\n");
 
-        for (auto noc_router : arch->noc->router_list) {
+        for (const auto& noc_router : arch->noc->router_list) {
             fprintf(Echo, "NoC router %d is connected to:\t", noc_router.id);
             for (auto noc_conn_id : noc_router.connection_list) {
                 fprintf(Echo, "%d\t", noc_conn_id);

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -41,16 +41,16 @@ using vtr::t_formula_data;
 /*---- Functions for Parsing Switchblocks from Architecture ----*/
 
 //Load an XML wireconn specification into a t_wireconn_inf
-t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches);
+static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector<t_arch_switch_inf>& switches);
 
 //Process the desired order of a wireconn
 static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order);
 
 //Process a wireconn defined in the inline style (using attributes)
-void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches);
+static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches);
 
 //Process a wireconn defined in the multinode style (more advanced specification)
-void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches);
+static void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches);
 
 //Process a <from> or <to> sub-node of a multinode wireconn
 t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiutil::loc_data& loc_data);
@@ -69,7 +69,7 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
 static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type);
 
 /* parse switch_override in wireconn */
-static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches);
+static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector<t_arch_switch_inf>& switches);
 
 /* checks for correctness of a unidir switchblock. */
 static void check_unidir_switchblock(const t_switchblock_inf* sb);
@@ -85,7 +85,7 @@ static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn);
 /*---- Functions for Parsing Switchblocks from Architecture ----*/
 
 /* Reads-in the wire connections specified for the switchblock in the xml arch file */
-void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
+void read_sb_wireconns(const std::vector<t_arch_switch_inf>& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
     /* Make sure that Node is a switchblock */
     check_node(Node, "switchblock", loc_data);
 
@@ -100,31 +100,29 @@ void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi
         SubElem = get_first_child(Node, "wireconn", loc_data);
     }
     for (int i = 0; i < num_wireconns; i++) {
-        t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches, num_switches); // need to pass in switch info for switch override
+        t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches); // need to pass in switch info for switch override
         sb->wireconns.push_back(wc);
         SubElem = SubElem.next_sibling(SubElem.name());
     }
-
-    return;
 }
 
-t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches) {
+static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector<t_arch_switch_inf>& switches) {
     t_wireconn_inf wc;
 
     size_t num_children = count_children(node, "from", loc_data, ReqOpt::OPTIONAL);
     num_children += count_children(node, "to", loc_data, ReqOpt::OPTIONAL);
 
     if (num_children == 0) {
-        parse_wireconn_inline(node, loc_data, wc, switches, num_switches);
+        parse_wireconn_inline(node, loc_data, wc, switches);
     } else {
         VTR_ASSERT(num_children > 0);
-        parse_wireconn_multinode(node, loc_data, wc, switches, num_switches);
+        parse_wireconn_multinode(node, loc_data, wc, switches);
     }
 
     return wc;
 }
 
-void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) {
+static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches) {
     //Parse an inline wireconn definition, using attributes
     expect_only_attributes(node, {"num_conns", "from_type", "to_type", "from_switchpoint", "to_switchpoint", "from_order", "to_order", "switch_override"}, loc_data);
 
@@ -156,10 +154,10 @@ void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_da
 
     // parse switch overrides if they exist:
     char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value();
-    parse_switch_override(char_prop, wc, switches, num_switches);
+    parse_switch_override(char_prop, wc, switches);
 }
 
-void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) {
+void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector<t_arch_switch_inf>& switches) {
     expect_only_children(node, {"from", "to"}, loc_data);
 
     /* get the connection style */
@@ -173,7 +171,7 @@ void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc
     parse_switchpoint_order(char_prop, wc.to_switchpoint_order);
 
     char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value();
-    parse_switch_override(char_prop, wc, switches, num_switches);
+    parse_switch_override(char_prop, wc, switches);
 
     size_t num_from_children = count_children(node, "from", loc_data);
     size_t num_to_children = count_children(node, "to", loc_data);
@@ -378,19 +376,17 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu
         /* get the next switchblock function */
         SubElem = SubElem.next_sibling(SubElem.name());
     }
-
-    return;
 }
 
-static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches) {
+static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector<t_arch_switch_inf>& switches) {
     // sentinel value to use default driving switch for the receiving wire type
     if (switch_override == std::string("")) {
         wireconn.switch_override_indx = DEFAULT_SWITCH; //Default
         return;
     }
 
     // iterate through the valid switch names in the arch looking for the requested switch_override
-    for (int i = 0; i < num_switches; i++) {
+    for (int i = 0; i < (int)switches.size(); i++) {
         if (0 == strcmp(switch_override, switches[i].name.c_str())) {
             wireconn.switch_override_indx = i;
             return;

libs/libarchfpga/src/parse_switchblocks.h

@@ -11,7 +11,7 @@
 void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
 
 /* Reads-in the wire connections specified for the switchblock in the xml arch file */
-void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
+void read_sb_wireconns(const std::vector<t_arch_switch_inf>& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data);
 
 /* checks for correctness of switch block read-in from the XML architecture file */
 void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch);

libs/libarchfpga/src/physical_types.h

@@ -1380,11 +1380,11 @@ class t_pb_graph_pin {
     float thld = std::numeric_limits<float>::quiet_NaN();    /* For sequential logic elements the hold time */
     float tco_min = std::numeric_limits<float>::quiet_NaN(); /* For sequential logic elements the minimum clock to output time */
     float tco_max = std::numeric_limits<float>::quiet_NaN(); /* For sequential logic elements the maximum clock to output time */
-    t_pb_graph_pin* associated_clock_pin = nullptr;          /* For sequentail elements, the associated clock */
+    t_pb_graph_pin* associated_clock_pin = nullptr;          /* For sequential elements, the associated clock */
 
     /* This member is used when flat-routing and has_choking_spot are enabled.
      * It is used to identify choke points.
-     * This is only valid for IPINs, and it only contain the pins that are reachable to the pin by a forwarding path.
+     * This is only valid for IPINs, and it only contains the pins that are reachable to the pin by a forwarding path.
      * It doesn't take into account feed-back connection.
      * */
     std::unordered_set<int> connected_sinks_ptc; /* ptc numbers of sinks which are directly or indirectly connected to this pin */
@@ -1708,7 +1708,7 @@ enum class BufferSize {
  *            parallel stream of pass transistors feeding into a buffer,     *
  *            we would expect an additional "internal capacitance"           *
  *            to arise when the pass transistor is enabled and the signal    *
- *            must propogate to the buffer. See diagram of one stream below: *
+ *            must propagate to the buffer. See diagram of one stream below: *
  *                                                                           *
  *                  Pass Transistor                                          *
  *                       |                                                   *
@@ -1823,7 +1823,7 @@ struct t_rr_switch_inf {
     SwitchType type() const;
 
     //Returns true if this switch type isolates its input and output into
-    //seperate DC-connected subcircuits
+    //separate DC-connected subcircuits
     bool buffered() const;
 
     //Returns true if this switch type is configurable
@@ -1852,9 +1852,9 @@ struct t_rr_switch_inf {
  *       particular placement macro.                                        *
  */
 struct t_direct_inf {
-    char* name;
-    char* from_pin;
-    char* to_pin;
+    std::string name;
+    std::string from_pin;
+    std::string to_pin;
     int x_offset;
     int y_offset;
     int sub_tile_offset;
@@ -1894,7 +1894,7 @@ struct t_wireconn_inf {
                                     *          elements (if 'from' is larger than 'to'), or in some elements of 'to' having
                                     *          no driving connections (if 'to' is larger than 'from').
                                     * 'to':    The number of generated connections is set equal to the size of the 'to' set.
-                                    *          This ensures that each element of the 'to' set has precisely one incomming connection.
+                                    *          This ensures that each element of the 'to' set has precisely one incoming connection.
                                     *          Note: this may result in 'from' elements driving multiple 'to' elements (if 'to' is
                                     *          larger than 'from'), or some 'from' elements driving to 'to' elements (if 'from' is
                                     *          larger than 'to')
@@ -1948,7 +1948,7 @@ struct t_switchblock_inf {
     e_directionality directionality; /* the directionality of this switchblock (unidir/bidir) */
 
     int x = -1; /* The exact x-axis location that this SB is used, meaningful when type is set to E_XY_specified */
-    int y = -1; /* The exact y-axis location that this SB is used, meanignful when type is set to E_XY_specified */
+    int y = -1; /* The exact y-axis location that this SB is used, meaningful when type is set to E_XY_specified */
 
     /* We can also define a region to apply this SB to all locations falls into this region using regular expression in the architecture file*/
     t_sb_loc_spec reg_x;
@@ -2059,10 +2059,9 @@ struct t_arch {
     int Fs;
     float grid_logic_tile_area;
     std::vector<t_segment_inf> Segments;
-    t_arch_switch_inf* Switches = nullptr;
-    int num_switches;
-    t_direct_inf* Directs = nullptr;
-    int num_directs = 0;
+
+    std::vector<t_arch_switch_inf> switches;
+    std::vector<t_direct_inf> Directs;
 
     t_model* models = nullptr;
     t_model* model_library = nullptr;

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -2374,15 +2374,13 @@ struct ArchReader {
         size_t num_switches = pip_timing_models.size() + 2;
         std::string switch_name;
 
-        arch_->num_switches = num_switches;
-
         if (num_switches > 0) {
-            arch_->Switches = new t_arch_switch_inf[num_switches];
+            arch_->switches.resize(num_switches);
         }
 
         float R, Cin, Cint, Cout, Tdel;
         for (size_t i = 0; i < num_switches; ++i) {
-            t_arch_switch_inf* as = &arch_->Switches[i];
+            t_arch_switch_inf* as = &arch_->switches[i];
 
             R = Cin = Cint = Cout = Tdel = 0.0;
             SwitchType type;