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When performing post-implementation timing analysis using OpenSTA, the generated netlist cannot use parameters since each module needs to correspond with a cell in a liberty file.

Added a command-line option which tells the netlist writer to not use parameters when generating the netlist. If a primitive cannot be generated without using parameters, it will error out.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool docs Documentation lang-cpp C/C++ code labels Apr 24, 2025
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@amin1377 FYI

@github-actions github-actions bot added the lang-hdl Hardware Description Language (Verilog/VHDL) label Apr 24, 2025
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LGTM; just one documentation tweak.

When performing post-implementation timing analysis using OpenSTA, the
generated netlist cannot use parameters since each module needs to
correspond with a cell in a liberty file.

Added a command-line option which tells the netlist writer to not use
parameters when generating the netlist. If a primitive cannot be
generated without using parameters, it will error out.
@AlexandreSinger AlexandreSinger merged commit 971da65 into verilog-to-routing:master Apr 29, 2025
36 checks passed
@AlexandreSinger AlexandreSinger deleted the feature-open-sta branch April 29, 2025 20:42
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3 participants