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After moving fixed blocks to the center of tiles, there is a very small chance that blocks go off the device due to rounding. This is such a small effect that it does not show up locally on my machine, but it shows up on CI. Clamping the positions of blocks after solving to be just within the device region.

This should fix the failure in the nightly tests.

After moving fixed blocks to the center of tiles, there is a very small
chance that blocks go off the device due to rounding. This is such a
small effect that it does not show up locally on my machine, but it
shows up on CI. Clamping the positions of blocks after solving to be
just within the device region.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Apr 28, 2025
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Thanks for the quick fix, Alex!

@AlexandreSinger AlexandreSinger merged commit f2b9bc2 into verilog-to-routing:master Apr 28, 2025
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@AlexandreSinger AlexandreSinger deleted the feature-ap-hot-fix branch April 28, 2025 19:14
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2 participants