[STA] Generating SDC Commands Post-Implementation #3016
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@vaughnbetz This is the PR which adds the ability to generate a post-implementation SDC file, as I presented at the meeting this afternoon. Based on the feedback, I have modified it to always set (non-virtual) clocks to propagated; even when the clock model is set to ideal. |
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| // Ideal and routed clocks are handled by the code below. Other clock models | ||
| // like dedicated routing are not supported yet. | ||
| if (clock_modeling != e_clock_modeling::ROUTED_CLOCK && clock_modeling != e_clock_modeling::IDEAL_CLOCK) { |
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I think this should work. We should already extract the delays and your code path presumably already writes those out as propagated clock delays.
Mustafa Abbas has some tests for routing dedicated clocks; you could find one of those and use it to test this functionality. If it works, remove the if.
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FYI, I tried this and it mostly worked by the CPD was off by 0.003 ns for the test circuit I used (the CLMA example with an H-tree clock network).
I am not sure where this discrepancy is coming from, the timing graph in open STA seems sounds; I think it may be an issue with the API calls used to parse the timing data from Tatum into the SDF file. Left a TODO to look into this so that this does not block this PR from getting merged.
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Sounds good. I'd enable it then. For the small difference: I agree it's not a blocking issue. I'd look closely at the clock path delays. Perhaps we have a min/max spread and openSTA is doing some clock pessimism removal or some such? If you get listings of the critical paths (including clock delays) in both flows I can go over it with you.
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Understood. I will raise an issue today to track this. The issue seemed to be caused by the edge delays of clocks reported by Tatum not matching what was written in the SDF file. All paths reported by OpenSTA were off by 0.003 ns.
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Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis.
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Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis.