Skip to content

Eliminate vtr_free and vtr_malloc/vtr_calloc/vtr_realloc #3040

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 5 commits into
base: master
Choose a base branch
from
+62 −76
Open

Eliminate vtr_free and vtr_malloc/vtr_calloc/vtr_realloc #3040

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
efd922c
removed most mallocs
SamuelHo10 May 13, 2025
2f679a7
Merge branch 'eliminate_free_and_malloc' of https://github.com/verilo…
SamuelHo10 May 13, 2025
0bdb49f
replaced most of the callocs with news
SamuelHo10 May 14, 2025
7cb2095
formatted c++
SamuelHo10 May 14, 2025
2c12600
undid a couple changes to fix odin memory leak
SamuelHo10 May 14, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
80 changes: 35 additions & 45 deletions libs/libarchfpga/src/arch_util.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,7 @@ void free_arch(t_arch* arch) {
vtr::free(arch->architecture_id);

if (arch->clocks) {
vtr::free(arch->clocks->clock_inf);
delete[] arch->clocks->clock_inf;
}

delete (arch->noc);
Expand Down Expand Up @@ -335,17 +335,17 @@ static void free_pb_type(t_pb_type* pb_type) {
for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) {
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]);
}
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].prop);
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value);
delete[] pb_type->modes[i].interconnect[j].annotations[k].prop;
delete[] pb_type->modes[i].interconnect[j].annotations[k].value;
}
vtr::free(pb_type->modes[i].interconnect[j].annotations);
delete[] pb_type->modes[i].interconnect[j].annotations;
if (pb_type->modes[i].interconnect[j].interconnect_power)
vtr::free(pb_type->modes[i].interconnect[j].interconnect_power);
delete pb_type->modes[i].interconnect[j].interconnect_power;
}
if (pb_type->modes[i].interconnect)
delete[] pb_type->modes[i].interconnect;
if (pb_type->modes[i].mode_power)
vtr::free(pb_type->modes[i].mode_power);
delete (pb_type->modes[i].mode_power);
}
if (pb_type->modes)
delete[] pb_type->modes;
Expand All @@ -354,8 +354,8 @@ static void free_pb_type(t_pb_type* pb_type) {
for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
vtr::free(pb_type->annotations[i].value[j]);
}
vtr::free(pb_type->annotations[i].value);
vtr::free(pb_type->annotations[i].prop);
delete[] pb_type->annotations[i].value;
delete[] pb_type->annotations[i].prop;
if (pb_type->annotations[i].input_pins) {
vtr::free(pb_type->annotations[i].input_pins);
}
Expand All @@ -371,7 +371,7 @@ static void free_pb_type(t_pb_type* pb_type) {
}

if (pb_type->pb_type_power) {
vtr::free(pb_type->pb_type_power);
delete pb_type->pb_type_power;
}

for (int i = 0; i < pb_type->num_ports; ++i) {
Expand All @@ -380,10 +380,10 @@ static void free_pb_type(t_pb_type* pb_type) {
vtr::free(pb_type->ports[i].port_class);
}
if (pb_type->ports[i].port_power) {
vtr::free(pb_type->ports[i].port_power);
delete pb_type->ports[i].port_power;
}
}
vtr::free(pb_type->ports);
delete[] pb_type->ports;
}

t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) {
Expand Down Expand Up @@ -495,13 +495,12 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->num_pb = 1;

/* Power */
copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1,
sizeof(t_pb_type_power));
copy->pb_type_power = new t_pb_type_power();
copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method);

/* Ports */
copy->num_ports = pb_type->num_ports;
copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
copy->ports = new t_port[pb_type->num_ports]();
for (i = 0; i < pb_type->num_ports; i++) {
copy->ports[i].is_clock = pb_type->ports[i].is_clock;
copy->ports[i].model_port = pb_type->ports[i].model_port;
Expand All @@ -514,8 +513,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->ports[i].index = pb_type->ports[i].index;
copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index;

copy->ports[i].port_power = (t_port_power*)vtr::calloc(1,
sizeof(t_port_power));
copy->ports[i].port_power = new t_port_power();
//Defaults
if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) {
copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO;
Expand Down Expand Up @@ -549,8 +547,8 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->annotations[i].format = pb_type->annotations[i].format;
copy->annotations[i].type = pb_type->annotations[i].type;
copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs;
copy->annotations[i].prop = (int*)vtr::malloc(sizeof(int) * pb_type->annotations[i].num_value_prop_pairs);
copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs);
copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs];
copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs];
for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) {
copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j];
copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]);
Expand Down Expand Up @@ -580,8 +578,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[0].parent_pb_type = lut_pb_type;
lut_pb_type->modes[0].index = 0;
lut_pb_type->modes[0].num_pb_type_children = 0;
lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
lut_pb_type->modes[0].mode_power = new t_mode_power();

/* Process interconnect */
/* TODO: add timing annotations to route-through */
Expand Down Expand Up @@ -613,10 +610,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0;
lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0];
lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power();

lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations,
sizeof(t_pin_to_pin_annotation));
lut_pb_type->modes[0].interconnect[0].annotations = new t_pin_to_pin_annotation[lut_pb_type->num_annotations]();
lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations;
for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations;
i++) {
Expand All @@ -627,10 +623,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs;
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = (int*)vtr::malloc(sizeof(int)
* lut_pb_type->annotations[i].num_value_prop_pairs);
lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*)
* lut_pb_type->annotations[i].num_value_prop_pairs);
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs];
lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs];
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j];
lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]);
Expand All @@ -643,30 +637,29 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[1].parent_pb_type = lut_pb_type;
lut_pb_type->modes[1].index = 1;
lut_pb_type->modes[1].num_pb_type_children = 1;
lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
lut_pb_type->modes[1].mode_power = new t_mode_power();
lut_pb_type->modes[1].pb_type_children = new t_pb_type[1];
alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name,
lut_pb_type->modes[1].pb_type_children);
/* moved annotations to child so delete old annotations */
for (i = 0; i < lut_pb_type->num_annotations; i++) {
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
free(lut_pb_type->annotations[i].value[j]);
vtr::free(lut_pb_type->annotations[i].value[j]);
}
free(lut_pb_type->annotations[i].value);
free(lut_pb_type->annotations[i].prop);
delete[] lut_pb_type->annotations[i].value;
delete[] lut_pb_type->annotations[i].prop;
if (lut_pb_type->annotations[i].input_pins) {
free(lut_pb_type->annotations[i].input_pins);
vtr::free(lut_pb_type->annotations[i].input_pins);
}
if (lut_pb_type->annotations[i].output_pins) {
free(lut_pb_type->annotations[i].output_pins);
vtr::free(lut_pb_type->annotations[i].output_pins);
}
if (lut_pb_type->annotations[i].clock) {
free(lut_pb_type->annotations[i].clock);
vtr::free(lut_pb_type->annotations[i].clock);
}
}
lut_pb_type->num_annotations = 0;
free(lut_pb_type->annotations);
vtr::free(lut_pb_type->annotations);
lut_pb_type->annotations = nullptr;
lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1;
lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1];
Expand Down Expand Up @@ -694,7 +687,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1;
lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1];
lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power();

lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char));
sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s",
Expand All @@ -713,7 +706,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1;
lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1];
lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power();

free(default_name);

Expand All @@ -738,8 +731,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
mem_pb_type->modes[0].name = vtr::strdup(default_name);
mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
mem_pb_type->modes[0].index = 0;
mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
mem_pb_type->modes[0].mode_power = new t_mode_power();
num_pb = OPEN;
for (i = 0; i < mem_pb_type->num_ports; i++) {
if (mem_pb_type->ports[i].port_class != nullptr
Expand Down Expand Up @@ -835,8 +827,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
}

/* Allocate interconnect power structures */
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
sizeof(t_interconnect_power));
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
i_inter++;
} else {
for (j = 0; j < num_pb; j++) {
Expand Down Expand Up @@ -876,8 +867,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
}

/* Allocate interconnect power structures */
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
sizeof(t_interconnect_power));
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
i_inter++;
}
}
Expand Down Expand Up @@ -944,7 +934,7 @@ void SyncModelsPbTypes_rec(t_arch* arch,

pb_type->model_id = model_match_prim_id;
vtr::t_linked_vptr* old = model_match_prim.pb_types;
model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr));
model_match_prim.pb_types = new vtr::t_linked_vptr;
model_match_prim.pb_types->next = old;
model_match_prim.pb_types->data_vptr = pb_type;

Expand Down
4 changes: 2 additions & 2 deletions libs/libarchfpga/src/echo_arch.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -383,7 +383,7 @@ static void print_model(FILE* echo, const t_model& model) {
static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) {
char* tabs;

tabs = (char*)vtr::malloc((level + 1) * sizeof(char));
tabs = new char[level + 1];
for (int i = 0; i < level; i++) {
tabs[i] = '\t';
}
Expand Down Expand Up @@ -455,7 +455,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
if (pb_type->pb_type_power) {
PrintPb_types_recPower(Echo, pb_type, tabs);
}
free(tabs);
delete[] tabs;
}

//Added May 2013 Daniel Chen, help dump arch info after loading from XML
Expand Down
2 changes: 1 addition & 1 deletion libs/libarchfpga/src/logic_types.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@ void LogicalModels::free_model_data(t_model& model) {
while (vptr) {
vtr::t_linked_vptr* vptr_prev = vptr;
vptr = vptr->next;
vtr::free(vptr_prev);
delete vptr_prev;
}

if (model.instances)
Expand Down
20 changes: 10 additions & 10 deletions libs/libarchfpga/src/read_fpga_interchange_arch.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -219,7 +219,7 @@ static t_port get_generic_port(t_arch* arch,
port.is_non_clock_global = false;
port.model_port = nullptr;
port.port_class = vtr::strdup(nullptr);
port.port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
port.port_power = new t_port_power();

if (!model.empty())
port.model_port = get_model_port(arch, model, name);
Expand All @@ -243,8 +243,8 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
t_pin_to_pin_annotation pp;

pp.prop = (int*)vtr::calloc(1, sizeof(int));
pp.value = (char**)vtr::calloc(1, sizeof(char*));
pp.prop = new int();
pp.value = new char*();

pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Expand Down Expand Up @@ -1293,7 +1293,7 @@ struct ArchReader {
lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);

lut->num_ports = 2;
lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port));
lut->ports = new t_port[lut->num_ports]();
lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width);
lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES);

Expand Down Expand Up @@ -1377,7 +1377,7 @@ struct ArchReader {
port->name = is_input ? vtr::strdup(ipin.c_str()) : vtr::strdup(opin.c_str());
port->model_port = nullptr;
port->port_class = vtr::strdup(nullptr);
port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
port->port_power = new t_port_power();
}

// OPAD mode
Expand All @@ -1395,7 +1395,7 @@ struct ArchReader {

num_ports = 1;
opad->num_ports = num_ports;
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
opad->ports = new t_port[num_ports]();
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);

Expand All @@ -1417,7 +1417,7 @@ struct ArchReader {

num_ports = 1;
ipad->num_ports = num_ports;
ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
ipad->ports = new t_port[num_ports]();
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);

Expand Down Expand Up @@ -1544,7 +1544,7 @@ struct ArchReader {

int num_ports = ic_count;
leaf->num_ports = num_ports;
leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
leaf->ports = new t_port[num_ports]();
leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str());
leaf->model_id = get_model(arch_, name);

Expand Down Expand Up @@ -2082,7 +2082,7 @@ struct ArchReader {
pb_type->modes = new t_mode[pb_type->num_modes];

pb_type->num_ports = 2;
pb_type->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
pb_type->ports = new t_port[pb_type->num_ports]();

pb_type->num_output_pins = 2;
pb_type->num_input_pins = 0;
Expand Down Expand Up @@ -2118,7 +2118,7 @@ struct ArchReader {

int num_ports = 1;
leaf_pb_type->num_ports = num_ports;
leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
leaf_pb_type->ports = new t_port[num_ports]();
leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str());
leaf_pb_type->model_id = get_model(arch_, const_cell.first);

Expand Down
Loading