[Bugfix][SM120] Enable CUTLASS grouped GEMM (MoE) for SM_120/SM_121 consumer Blackwell

[tgmerritt]

Summary

Fixes two bugs that silently disabled the CUTLASS FP8 grouped GEMM path for all SM_120/SM_121 hardware (RTX 5090/5080/5070, DGX Spark GB10), causing every MoE expert dispatch to fall back to the Triton backend.

Fixes #43507.

---

What changed

Bug 1 — Python gate (vllm/_custom_ops.py)

# Before (wrong):
if cuda_device_capability < 90 or cuda_device_capability >= 110:
    return False

# After (correct):
if cuda_device_capability < 90 or cuda_device_capability >= 130:
    return False

cuda_device_capability is an integer: 121 >= 110 is True, so this gate always returned False for SM121, routing every call through Triton. >= 130 is correct — it reserves the exit clause for genuinely unsupported future architectures beyond SM12x.

Bug 2 — Missing SM120 grouped GEMM kernel

Added csrc/libtorch_stable/quantization/w8a8/cutlass/moe/grouped_mm_c3x_sm120.cu, the SM120 analog of grouped_mm_c3x_sm100.cu. Configuration:

• Schedule: KernelPtrArrayTmaWarpSpecializedCooperativeSm120<2> (cooperative, 4×2 UMMA atom layout)
• Tile shape: 128×128×128 (same as SM100 default)
• Cluster shape: 1×1×1 (no programmatic multicast on consumer Blackwell)
• Epilogue: EpilogueScheduleAuto (auto-selects per-tensor/per-token scaling in the epilogue, matching the FP8-Dynamic quantization scheme)
• Arch tag: Sm120 (runs on SM_121 as well per CUDA arch compatibility)

Added dispatch block in scaled_mm_entry.cu for version_num >= 120 && version_num < 130.
Added the .cu file to the existing SM12x build block in CMakeLists.txt (under FP4_ARCHS, which already sets ENABLE_CUTLASS_MOE_SM120=1).

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CUTLASS dependency

KernelPtrArrayTmaWarpSpecializedCooperativeSm120<2> requires the MainloopSm120ArrayTmaWarpSpecialized collective specialization, which is not yet in CUTLASS 4.5. It has been contributed upstream via NVIDIA/cutlass#3280 (currently in review). This vLLM PR will compile correctly once vLLM's pinned CUTLASS revision includes that change.

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Why not duplicate

• gh pr list --repo vllm-project/vllm --state open --search "SM121 cuda_device_capability" — no results
• gh pr list --repo vllm-project/vllm --state open --search "grouped_mm_c3x_sm120" — no results
• Existing SM120 PRs (Enable DeepSeek V4 and GLM-5.1 on SM120 #43477, Add SM120 for NVFP4 tensor core support #41738, [Bugfix] Reduce sparse-MLA + indexer workspace bounds on SM_120 (consumer Blackwell) #42856) address different subsystems (FlashInfer, NVFP4, sparse-MLA), not the FP8 grouped GEMM path

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Hardware validation

Validated on SM_121 hardware (NVIDIA DGX Spark, GB10, 128 GB LPDDR5X unified memory):

• Container: vLLM source build, CUDA 13.0.2, TORCH_CUDA_ARCH_LIST=12.0a;12.1a;12.1+PTX, patched CUTLASS (includes [SM120] Add ptr-array TMA collective for tensor/token-scaled FP8 grouped GEMM NVIDIA/cutlass#3280 changes)
• Model: RedHatAI/gemma-4-26B-A4B-it-FP8-Dynamic (Gemma 4 MoE, 26B total / 4B active, FP8-Dynamic quantization)

Result: SM120 CUTLASS grouped GEMM collective activates and produces correct outputs. Previously fell back to Triton for every MoE dispatch.

Throughput comparison (wall-clock, single-stream, MTP speculative decoding, 3 iterations)

Prompt size	Baseline (Triton fallback)	This fix (SM120 CUTLASS)	Delta
Short (128 tok output)	76.3 tok/s	81.9 tok/s	+7.3%
Medium (512 tok output)	89.8 tok/s	89.8 tok/s	≈0% (within noise)
Long (1024 tok output)	87.6 tok/s	85.5 tok/s	-2.4% (within noise)

Short-sequence improvement is the clearest signal (decode-dominated, grouped GEMM runs every forward pass). Medium/long variance is dominated by speculative decoding accept-rate noise over 3 iterations.

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AI assistance disclosure

This fix was developed with Claude (Anthropic) AI assistance, including root cause analysis of the gate condition, derivation of the SM120 kernel configuration from the SM100 analog, and iterative compile debugging (four full Docker builds on real SM_121 hardware). All changed lines have been reviewed by the human submitter (Tyler Merritt). Build and inference validation ran on physical DGX Spark hardware.

Related CUTLASS upstream PR: NVIDIA/cutlass#3280

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[mergify]

Hi @tgmerritt, the pre-commit checks have failed. Please run:

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[tgmerritt]

Pre-commit checks ran locally against all changed files and passed:

ruff check        Passed
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The CI pre-run-check failure is the new-contributor gate (0 merged PRs). Happy to address any review feedback once a maintainer can add the ready label.