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[Bugfix] Pad unaligned N in SM12x CUTLASS blockwise FP8 GEMM#48588

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[Bugfix] Pad unaligned N in SM12x CUTLASS blockwise FP8 GEMM#48588
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jszzr:fix-sm120-block-fp8-unaligned-n

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@jszzr jszzr commented Jul 14, 2026

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Purpose

Fixes #47990.

The SM120 CUTLASS c3x blockwise FP8 GEMM rejects every problem whose weight output dim N is not a multiple of 128: all three tile configs in scaled_mm_blockwise_sm120_fp8_dispatch.cuh fail CUTLASS can_implement. N=576 is kv_a_proj_with_mqa (512+64) in DeepSeek-V3-family models, so any block-FP8 DeepSeek-shaped checkpoint crashes at engine startup with cutlass_gemm_caller ... Invalid status whenever the layer routes to the CUTLASS kernel (e.g. wherever DeepGEMM is unavailable or auto-disabled on SM12x, see #47436 / #47169).

This implements the padding remediation suggested in the issue: zero-pad the weight N to the next multiple of 128 once at load time, and slice the padded columns off after the GEMM. The padded rows land inside the last, already-present scale block (checkpoint scales have ceil(N/128) rows), so the scale tensor needs no change. This is the same pattern CutlassFP8ScaledMMLinearKernel already uses for its 16-element alignment padding, and NVFP4 uses via pad_nvfp4_weight_for_cutlass.

Changes:

  • scaled_mm/cutlass.py: move the _pad_to_alignment / padded_weight_loader helpers from CutlassFP8ScaledMMLinearKernel to module scope so both CUTLASS kernels share them; CutlassFp8BlockScaledMMKernel.process_weights_after_loading pads N on SM12x (installing padded_weight_loader so weight reloads keep working) and apply_block_scaled_mm slices the output back to the logical width; the module-level cutlass_scaled_mm wrapper (test surface) pads per call.
  • scaled_mm/BlockScaledMMLinearKernel.py: the base apply_weights derives the logical output width from config.weight_shape[0] instead of weight.shape[0], since the weight may now carry padding.
  • tests/kernels/quantization/test_block_fp8.py: parametrize test_w8a8_block_fp8_cutlass_matmul over M x (N, K) including the previously-failing N=576 / N=2112 plus an aligned control, and add a layer-level test covering load-time padding, output slicing, bias, and a 3D input, compared head-to-head against TritonFp8BlockScaledMMKernel (both share the base apply_weights and QuantFP8, isolating the GEMM and pad/slice).

Why padding instead of falling back to Triton

#47988 adds a selection-level guard that declines unaligned N on SM12x so those layers fall through to Triton. That is correct for safety, but keeps DeepSeek-shaped layers off the faster kernel. Measured on an RTX PRO 5000 Blackwell (SM120, CUDA 13.0, torch 2.11.0+cu130), padded CUTLASS including the output-slice copy vs w8a8_triton_block_scaled_mm (default config; no tuned JSON exists for this device):

M N=576, K=7168 (kv_a_proj) N=2112, K=1536
1 21.5 us vs 57.6 us (2.68x) 21.0 us vs 33.2 us (1.58x)
16 25.8 us vs 59.6 us (2.31x) 25.0 us vs 35.9 us (1.44x)
64 24.8 us vs 71.2 us (2.87x) 25.0 us vs 34.5 us (1.38x)
256 30.8 us vs 59.7 us (1.93x) 25.0 us vs 33.2 us (1.33x)
1024 55.4 us vs 61.6 us (1.11x) 32.9 us vs 34.0 us (1.03x)
4096 110.8 us vs 147.7 us (1.33x) 81.1 us vs 89.8 us (1.11x)

Correctness sweep vs the fp32-dequant native reference: rel err <= 2e-8 across M in {1, 32, 83, 256} x N in {576, 2112}, identical to Triton's error.

If this lands, the SM12x N % 128 guard in #47988 becomes unnecessary (its E8M0 handling is orthogonal and still needed) — happy to coordinate, cc @waynehacking8.

The remaining kernel-level gap (native ragged-N support in the CUTLASS SM120 blockwise collectives) is upstream CUTLASS work; padding at the integration layer costs at most 127 zero columns on a single projection (64 x 7168 FP8 = 448 KiB for DeepSeek's kv_a_proj).

Test Plan

All executed on RTX PRO 5000 Blackwell (SM120), CUDA 13.0, torch 2.11.0+cu130, precompiled kernels at merge-base:

  • pytest tests/kernels/quantization/test_block_fp8.py -k cutlass: 10 passed (the N=576 case fails on current main with Invalid status).
  • Full test_block_fp8.py: no new failures (the pre-existing SM120 DeepGEMM failures are identical on clean main).
  • pytest tests/kernels/quantization/test_cutlass_scaled_mm.py -k fp8: 261 passed (validates the helper refactor; the file's int8 tests fail on SM120 with "Int8 not supported on SM120" both before and after this change).
  • pre-commit (ruff check/format, typos, SPDX, etc.) and mypy clean on the changed files.
  • E2E A/B with a tiny DeepSeek-V3-arch block-FP8 config (kv_a_proj_with_mqa N=576, --load-format dummy, --linear-backend cutlass, dense-only to avoid unrelated SM120 MoE issues):
    • main: Selected CutlassFp8BlockScaledMMKernel for Fp8LinearMethod -> EngineCore failed to start ... RuntimeError: cutlass_gemm_caller ... Invalid status
    • this PR: same selection -> startup completes and generation works.

Test Result

See above; all listed tests pass on SM120 hardware.


AI tooling assisted with this change; I reviewed all changes and ran every test and benchmark above on my own SM120 hardware.

…oject#47990)

The SM120 CUTLASS blockwise FP8 kernels reject every problem whose
weight output dim N is not a multiple of the 128x128 scale block
(CUTLASS can_implement fails for all three tile configs), so any
DeepSeek-shaped block-FP8 checkpoint (kv_a_proj_with_mqa N=576)
crashes on engine startup once the layer routes to the CUTLASS kernel.

Zero-pad N to the scale block at weight load time and slice the
padding off after the GEMM, following the pattern the per-tensor
CUTLASS FP8 kernel already uses for its 16-element alignment. The
padded rows land in the last, already-present scale block, so the
scale tensor needs no change. The shared padding helpers move to
module scope, and the block kernel base derives the logical output
width from the layer config instead of the (possibly padded) weight.

Padded CUTLASS is 1.9-2.9x faster than the Triton fallback at decode
batch sizes on the DeepSeek kv_a_proj shape, measured on an RTX PRO
5000 Blackwell.

Fixes vllm-project#47990

Signed-off-by: Zhirui <69025003+jszzr@users.noreply.github.com>

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Verified on a second SM120 device (RTX PRO 6000 Blackwell Max-Q, CUDA 13.0, torch 2.11.0+cu130): the -k cutlass selection of test_block_fp8.py fails on current main with the exact Invalid status from #47990 and passes all 10 on this branch, and re-running my shape sweep from the issue through the patched wrapper (fp32-dequant reference, N in {64, 192, 576, 2112} x M up to 1024) gives 2-3e-3 rel err everywhere, same as aligned shapes. Perf direction matches here too: padded CUTLASS including the slice copy beat the default-config Triton fallback at every M I tried on the kv_a_proj shape, ~1.4-2.3x at decode-ish M (co-tenanted box, so take the exact ratios loosely). Agreed on the #47988 interaction: I'll keep the N%128 guard there until this lands, then drop it and keep only the E8M0 upcast -- the two PRs collide textually in cutlass.py, so whoever lands second rebases, happy for that to be me.

@jszzr

jszzr commented Jul 14, 2026

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Thanks for the independent verification on a second SM120 device @waynehacking8! Full CI is currently gated on the first-contribution pre-run-check — would appreciate a maintainer adding the ready label to kick off the test run. Happy to address anything that comes back.

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[Bug]: SM120 CUTLASS blockwise FP8 GEMM rejects N % 128 != 0 (Invalid status; kv_a_proj N=576 in DeepSeek shapes)

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