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Smaller fixes and improvements #2

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Smaller fixes and improvements #2

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3eff480
[config] Fix help string
wallento Jan 25, 2019
3717ed9
[structure] Rename SystemVerilog to sv
wallento Jan 25, 2019
091e09b
[structure] Move types to package
wallento Jan 27, 2019
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2 changes: 1 addition & 1 deletion configs/swerv.config
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Expand Up @@ -99,7 +99,7 @@ User options:

Additional direct options for the following variables:

-ret_size = {2, 3, 4, ... 8}
-ret_stack_size = {2, 3, 4, ... 8}
size of return stack
-btb_size = { 32, 48, 64, 128, 256, 512 }
size of branch target buffer
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1 change: 1 addition & 0 deletions design/dec/dec.sv
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Expand Up @@ -28,6 +28,7 @@
//********************************************************************************

module dec
import swerv_types::*;
(
input logic clk,
input logic free_clk,
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2 changes: 2 additions & 0 deletions design/dec/dec_decode_ctl.sv
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Expand Up @@ -15,6 +15,7 @@


module dec_decode_ctl
import swerv_types::*;
(
input logic [15:0] dec_i0_cinst_d, // 16b compressed instruction
input logic [15:0] dec_i1_cinst_d,
Expand Down Expand Up @@ -2430,6 +2431,7 @@ endmodule
// 2) espresso -Dso -oeqntott legal.e | addassign -pre out. > legal_equation

module dec_dec_ctl
import swerv_types::*;
(
input logic [31:0] inst,

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1 change: 1 addition & 0 deletions design/dec/dec_ib_ctl.sv
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Expand Up @@ -14,6 +14,7 @@
// limitations under the License.

module dec_ib_ctl
import swerv_types::*;
(
input logic free_clk, // free clk
input logic active_clk, // active clk if not halt / pause
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1 change: 1 addition & 0 deletions design/dec/dec_tlu_ctl.sv
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Expand Up @@ -24,6 +24,7 @@
//********************************************************************************

module dec_tlu_ctl
import swerv_types::*;
(
input logic clk,
input logic active_clk,
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8 changes: 5 additions & 3 deletions design/dec/dec_trigger.sv
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Expand Up @@ -22,9 +22,11 @@
// Comments:
//
//********************************************************************************
module dec_trigger (
input logic clk,
input logic rst_l,
module dec_trigger
import swerv_types::*;
(
input logic clk,
input logic rst_l,

input trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match
input logic [31:1] dec_i0_pc_d, // i0 pc
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0 design/dmi/rvjtag_tap.v → design/dmi/rvjtag_tap.sv
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1 change: 1 addition & 0 deletions design/exu/exu.sv
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Expand Up @@ -15,6 +15,7 @@


module exu
import swerv_types::*;
(

input logic clk, // Top level clock
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1 change: 1 addition & 0 deletions design/exu/exu_alu_ctl.sv
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Expand Up @@ -15,6 +15,7 @@


module exu_alu_ctl
import swerv_types::*;
(
input logic clk, // Top level clock
input logic active_clk, // Level 1 free clock
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1 change: 1 addition & 0 deletions design/exu/exu_div_ctl.sv
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Expand Up @@ -15,6 +15,7 @@


module exu_div_ctl
import swerv_types::*;
(
input logic clk, // Top level clock
input logic active_clk, // Level 1 active clock
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1 change: 1 addition & 0 deletions design/exu/exu_mul_ctl.sv
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Expand Up @@ -15,6 +15,7 @@


module exu_mul_ctl
import swerv_types::*;
(
input logic clk, // Top level clock
input logic active_clk, // Level 1 active clock
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71 changes: 36 additions & 35 deletions design/flist.spyglass
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@@ -1,45 +1,46 @@
$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/swerv_types.sv
$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/dec/dec_tlu_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/lsu_stbuf.sv
$RV_ROOT/design/lsu/lsu_bus_read_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_write_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_intf.sv
$RV_ROOT/design/lsu/lsu_ecc.sv
$RV_ROOT/design/lsu/lsu_dccm_mem.sv
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
$RV_ROOT/design/dmi/double_flop_sync.v
$RV_ROOT/design/dmi/toggle_sync.v
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv
2 changes: 1 addition & 1 deletion design/flist.vcs
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Expand Up @@ -36,7 +36,7 @@ $RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
$RV_ROOT/design/dmi/double_flop_sync.v
$RV_ROOT/design/dmi/toggle_sync.v
$RV_ROOT/design/lib/beh_lib.sv
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71 changes: 36 additions & 35 deletions design/flist.verilator
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@@ -1,45 +1,46 @@
$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/lib/swerv_types.sv
$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/dec/dec_tlu_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/lsu_stbuf.sv
$RV_ROOT/design/lsu/lsu_bus_read_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_write_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_intf.sv
$RV_ROOT/design/lsu/lsu_ecc.sv
$RV_ROOT/design/lsu/lsu_dccm_mem.sv
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
$RV_ROOT/design/dmi/double_flop_sync.v
$RV_ROOT/design/dmi/toggle_sync.v
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv
2 changes: 1 addition & 1 deletion design/flist.vlog
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Expand Up @@ -36,7 +36,7 @@ $RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
$RV_ROOT/design/dmi/double_flop_sync.v
$RV_ROOT/design/dmi/toggle_sync.v
$RV_ROOT/design/lib/beh_lib.sv
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1 change: 1 addition & 0 deletions design/ifu/ifu.sv
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Expand Up @@ -20,6 +20,7 @@
//********************************************************************************

module ifu
import swerv_types::*;
(
input logic free_clk,
input logic active_clk,
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1 change: 1 addition & 0 deletions design/ifu/ifu_aln_ctl.sv
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Expand Up @@ -19,6 +19,7 @@
// Function: Instruction aligner
//********************************************************************************
module ifu_aln_ctl
import swerv_types::*;
(

input logic active_clk,
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5 changes: 3 additions & 2 deletions design/ifu/ifu_bp_ctl.sv
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Expand Up @@ -17,14 +17,15 @@

//********************************************************************************
// Function: Branch predictor
// Comments:
//
// Comments:
//
//
// Bank3 : Bank2 : Bank1 : Bank0
// FA C 8 4 0
//********************************************************************************

module ifu_bp_ctl
import swerv_types::*;
(

input logic clk,
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3 changes: 2 additions & 1 deletion design/ifu/ifu_mem_ctl.sv
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Expand Up @@ -21,7 +21,8 @@
// BFF -> F1 -> F2 -> A
//********************************************************************************

module ifu_mem_ctl
module ifu_mem_ctl
import swerv_types::*;
(
input logic clk,
input logic free_clk, // free clock always except during pause
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