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xiaokamikami/README.md

๐Ÿ‘‹ Hi, I'm xiaokamikami

๐Ÿ”Œ FPGA & IC Design Engineer | ๅตŒๅ…ฅๅผๅทฅ็จ‹ๅธˆ

GitHub followers QQ


๐Ÿš€ About Me

๐ŸŽ‚ Born in 2002.08.05 | ๐Ÿ’ก Passionate about Digital Circuit Design

"From embedded systems to siliconโ€”building the hardware of tomorrow"

I'm an embedded engineer and IC design enthusiast, specializing in FPGA development and digital chip design. Currently exploring the fascinating world of hardware acceleration and custom silicon.

๐Ÿ’ป Tech Stack

Languages & HDL

Verilog C C++ Python

FPGA & Tools

  • FPGA Platforms: Xilinx (Vivado, Vitis), Altera/Intel (Quartus)
  • Simulation: ModelSim, Vivado Simulator, Verilator
  • Design: SystemVerilog, Verilog HDL
  • Protocols: AXI, UART, SPI, I2C, PCIe
  • Embedded: ARM Cortex, RISC-V

๐Ÿ”ญ Current Focus

  • ๐Ÿ”ฌ Deep diving into advanced FPGA architectures
  • ๐Ÿง  Exploring AI/ML acceleration on FPGA
  • ๐Ÿš€ Building high-performance computing solutions
  • ๐Ÿ“ก Developing communication protocol IPs

๐Ÿ“Š GitHub Stats

GitHub Stats

Top Languages

๐ŸŽฏ Areas of Expertise

Domain Technologies
FPGA Design RTL Design, Timing Closure, Resource Optimization
IC Verification Testbench Development, Coverage Analysis
Embedded Systems Microcontroller Programming, RTOS
Digital Signal Processing FIR/IIR Filters, FFT Implementation
Hardware Acceleration Custom Computing Architecture

๐ŸŒฑ Learning Journey

  • Advanced Verification Methodologies (UVM)
  • High-Level Synthesis (HLS)
  • ASIC Design Flow
  • Formal Verification
  • Computer Architecture Optimization

๐Ÿ’ก Project Highlights

๐Ÿ“ฆ Featured Repositories
โ”‚
โ”œโ”€โ”€ ๐Ÿ”ง FPGA IP Cores
โ”‚   โ””โ”€โ”€ Custom designed and verified IP blocks
โ”‚
โ”œโ”€โ”€ ๐ŸŽฎ Embedded Projects
โ”‚   โ””โ”€โ”€ Microcontroller-based applications
โ”‚
โ””โ”€โ”€ ๐Ÿงช Design Examples
    โ””โ”€โ”€ Learning projects and experiments

๐Ÿ“ซ Let's Connect

QQ GitHub


๐Ÿ’ฌ "Hardware is hard, but the journey is rewarding"

Visitor Count

โญ๏ธ From xiaokamikami | Building the future, one clock cycle at a time โšก

Pinned Loading

  1. OpenXiangShan/XiangShan OpenXiangShan/XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 6.8k 837

  2. OpenXiangShan/difftest OpenXiangShan/difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 159 86

  3. vivado_dma_send vivado_dma_send Public

    Tcl

  4. ysyx-npc ysyx-npc Public

    C 8 2

  5. dma-test dma-test Public

    C++ 1

  6. Bin2ddr Bin2ddr Public

    C++ 1