You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
CSE 531 Computer Security project — Flush+Reload cache side-channel reproduced
across six CPU microarchitectures, with two attack scenarios and a CWE
taxonomy mapping.
Architectures measured
Architecture
CPU
Environment
Intel Raptor Lake (client hybrid)
i7-13700
Ubuntu Linux
Intel Sapphire Rapids (server)
Xeon w9-3495X
Ubuntu Linux
Intel Alder Lake-N (low-power)
N150
Ubuntu Linux
AMD Zen 3
Ryzen 5 5600X
Ubuntu on WSL2
Apple Silicon
M3 Pro
macOS
ARM Neoverse N2
Azure Cobalt 100 (Dpsv6)
Ubuntu Linux (Azure VM, spun up + torn down via Azure CLI)
Status
Milestone
State
1. Latency-histogram calibration
done on all 6 archs
2. Covert-channel PoC + bandwidth/BER sweep
done on all 6 archs
3. Side-channel key-recovery PoC
done; 20-run stats CSV captured
4. CWE-1194 taxonomy table
done (18 attacks mapped)
5. Report (IEEE 2-column)
done
6. Slide deck
done
Quick build (Linux x86 / Linux ARM)
sudo apt-get install -y build-essential python3-matplotlib
make
On Apple Silicon (macOS) the same make works — the covert_common.h
header dispatches automatically (Linux ARM uses native DC CIVAC + 1 GHz
CNTVCT; Apple Silicon falls back to an eviction-based flush + helper-thread
counter, since DC CIVAC is a userspace no-op on Apple).
Binaries
Binary
Role
latency_histogram
Calibration: prints HIT/MISS cycle CSV for one cache line.
sender / receiver
Covert-channel pair. 64-bit preamble auto-calibrates threshold; train BER and held-out BER reported separately.
victim_keyed / spy_keyed
Side-channel key-recovery PoC. Victim loops a hardcoded 128-bit secret; spy phase-locks on a "kick" line (RSA-routine-entry analogue) and reconstructs the key by majority vote.
WSL2 (Zen 3) measurements run inside a Hyper-V VM — cache topology and
scheduler jitter differ from bare metal. Documented in the comparison
section.
Apple M3 Pro: covert channel works at only ~10-50 bps; eviction-based
flush is high-overhead and Apple's DMP prefetcher repopulates lines.
Cloud Neoverse N2: 2 vCPU shared-tenant VM adds noise; the BER trend is
representative, the absolute numbers are not bare-metal-grade.
Sapphire Rapids cross-core-far (CPU 0 ↔ 55): an initial run showed
~40-60 % BER that first looked like a mesh-interconnect distance penalty,
but repeated runs traced it to co-tenant load on the shared workstation —
not interconnect distance. When the machine is idle, every pair (including
the far corner) is clean. Detailed in the report's comparison section.
Threshold calibration: the receiver computes its threshold from the
first half of the preamble and reports held-out BER on the second half,
separating training error from generalisation error.
About
Cross-architecture Flush+Reload reproduction on six modern CPUs (CSE 531 course project)