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stm32cube: stm32f4, stm32f7: Fix errata workaround #362

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stm32cube: stm32f4, stm32f7: Fix errata workaround #362

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5 changes: 5 additions & 0 deletions stm32cube/stm32f4xx/README
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Original file line number Diff line number Diff line change
Expand Up @@ -60,4 +60,9 @@ Patch List:
Impacted files:
drivers/include/stm32f4xx_ll_fsmc.h
ST Internal Reference: 223859

*Fix missing errata workaround after writing RE in ETH->MACCR
Impacted files:
drivers/src/stm32f4xx_hal_eth.c

See release_note.html from STM32Cube
6 changes: 3 additions & 3 deletions stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
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Original file line number Diff line number Diff line change
Expand Up @@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
/* Enable the MAC transmission */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);

/* Enable the MAC reception */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);

/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;

/* Enable the MAC reception */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);

/* Enable ETH DMA interrupts:
- Tx complete interrupt
- Rx complete interrupt
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4 changes: 4 additions & 0 deletions stm32cube/stm32f7xx/README
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Original file line number Diff line number Diff line change
Expand Up @@ -55,4 +55,8 @@ Patch List:
Impacted files:
drivers/include/Legacy/stm32_hal_legacy.h

*Fix missing errata workaround after writing RE in ETH->MACCR
Impacted files:
drivers/src/stm32f7xx_hal_eth.c

See release_note.html from STM32Cube
6 changes: 3 additions & 3 deletions stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
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Original file line number Diff line number Diff line change
Expand Up @@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
/* Enable the MAC transmission */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);

/* Enable the MAC reception */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);

/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;

/* Enable the MAC reception */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);

/* Enable ETH DMA interrupts:
- Tx complete interrupt
- Rx complete interrupt
Expand Down
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