crc32 ambiq add driver#110366
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Bump hal_ambiq revision to 72007192ac28e0e7484a44a0b9ff3a31d08a5b28 to pull in the CRC32 boundary-safe HAL extensions required by the Ambiq Apollo510 hardware CRC driver: - am_hal_crc() with automatic TCM/SSRAM boundary splitting - am_hal_crc_find_next_boundary() helper - am_hal_crc_set_init() / am_hal_crc_finalize() for streaming CRC - SSRAM boundary macros in am_reg_base_addresses.h - am_hal_security.c added to apollo510 CMakeLists.txt Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Add devicetree binding for the Ambiq hardware CRC32 module. The binding describes a hardware-based CRC32 calculation peripheral and requires a reg property. Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Add hardware CRC32 peripheral node to the Ambiq Apollo510 device tree include file. The node is disabled by default and placed in the crypto power domain. Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
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zephyrbot
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area: Samples
zephyrbot
requested review from
AlessandroLuo,
JarmouniA,
aaronyegx,
kartben,
nashif,
nordicjm,
sylvioalves and
thenguyenyf
Add a hardware-accelerated CRC32 IEEE driver for Ambiq Apollo510 SoCs using the SECURITY peripheral. The driver implements the Zephyr streaming CRC API (begin/update/finish) with the following features: - Supports CRC32_IEEE only (0x04C11DB7, reflected input/output) - Configurable seed for chained/incremental calculations - Boundary-aware DMA splits at TCM 4 KB and memory region crossings - 32-byte cache-line aligned DMA with staging buffer fallback for unaligned input - Power managed via CRYPTO power domain using pm_device_runtime - Binary semaphore serialises concurrent CRC sessions New files: - drivers/crc/crc_ambiq.c: driver implementation - drivers/crc/Kconfig.ambiq: Kconfig symbol CRC_AMBIQ Updated files: - drivers/crc/Kconfig: source Kconfig.ambiq - drivers/crc/CMakeLists.txt: add crc_ambiq.c under CONFIG_CRC_AMBIQ Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Enable the hardware CRC32 peripheral on the Apollo510 EVB board: - Add SPDX license header to apollo510_evb.dts - Add zephyr,crc chosen node pointing to &crc32 - Add crc0 alias for the CRC32 node - Enable &crc32 node (status = "okay") - Add crc to supported features in apollo510_evb.yaml - Add board Kconfig fragment for the CRC sample selecting CRC32_IEEE variant and disabling CRC8 Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
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drivers: crc: add Ambiq Apollo510 hardware CRC32 driver
Add hardware-accelerated CRC32 IEEE driver support for the Ambiq
Apollo510 SoC using the SECURITY peripheral. Changes across the
stack:
west.yml: bump hal_ambiq to add CRC32 HAL extensions
(am_hal_crc, am_hal_crc_find_next_boundary, am_hal_crc_set_init,
am_hal_crc_finalize, SSRAM boundary macros)
dts/bindings: new ambiq,hw-crc32 binding
dts/arm/ambiq: add crc32 node to Apollo510 DTSI (disabled)
drivers/crc: Ambiq CRC driver with streaming API, DMA cache
alignment, TCM/SSRAM boundary splitting, and pm_device_runtime
power management
boards/ambiq/apollo510_evb: enable crc32 node, add chosen and
alias, add crc to supported features
samples/drivers/crc: Apollo510 EVB board fragment enabling
CRC32_IEEE variant
HAL Update:
hal: ambiq: apollo510: add CRC boundary-safe HAL extensions hal_ambiq#65