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spi: zynq: Add Zynq 7000 Quad SPI driver - #113254

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spi: zynq: Add Zynq 7000 Quad SPI driver#113254
mausys wants to merge 1 commit into
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@mausys

@mausys mausys commented Jul 10, 2026

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Add a driver for the Xilinx Zynq 7000 Quad SPI controller. Note that while the hardware supports legacy SPI, this driver only supports flash mode.

@mausys
mausys force-pushed the zynq_qspi branch 9 times, most recently from d529d1f to 6917da5 Compare July 15, 2026 06:30
@mausys

mausys commented Jul 15, 2026

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Tested erase, write, and read operations with the Micron N25Q256A11 flash. Quad SPI has not been tested yet, as the spi-nor driver doesn't support it.

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mausys marked this pull request as ready for review July 15, 2026 06:48
@zephyrbot zephyrbot added area: Devicetree Binding PR modifies or adds a Device Tree binding area: SPI SPI bus platform: Xilinx AMD Xilinx labels Jul 15, 2026

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Fix the CI failures

interrupts:
required: true

clock-frequency:

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The binding makes clock-frequency required, but the driver never reads
clock-frequency. It obtains the reference rate at runtime via
clock_control_get_rate(config->clock_dev, ...), where clock_dev comes from
DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)) (driver line ~596) — i.e. it depends on a clocks
property. That clocks property is not declared/required by the binding, and the in-tree
node added to dts/arm/xilinx/zynq7000.dtsi has neither clocks nor clock-frequency.
Consequently: (a) any board that enables this node following the binding (adding only
clock-frequency) will fail to build because DT_INST_CLOCKS_CTLR(n) has no phandle to resolve;
(b) clock-frequency is dead/unused. Note clock-frequency is already inherited from
spi-controller.yaml, so re-declaring it as required here is also redundant. remove it from the bindings if driver is not using it

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Fixed. I have updated the driver to actually use the clock-frequency property now.

I would have preferred to use clock_control_get_rate(), but the Zynq 7000 clock control driver PR (#64996) unfortunately went stale. Because we currently lack a runtime clock controller for this platform, falling back to a static clock-frequency is the most viable path forward.

Once a proper clock control driver is upstreamed, we can refactor this driver to query it at runtime.

Comment thread drivers/spi/Kconfig.xlnx_zynq_qspi Outdated
bool "Xilinx Zynq Quad SPI driver"
default y
depends on DT_HAS_XLNX_ZYNQ_QSPI_ENABLED
select EVENTS

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select EVENTS appears unnecessary — the driver uses spi_context (semaphore-based
sync via SPI_CONTEXT_INIT_SYNC / spi_context_wait_for_completion) and contains no k_event
usage; spi_context.h does not use the events API either. (The sibling Kconfig.xlnx and
Kconfig.xlnx_zynqmp_gqspi also select EVENTS, so this looks copy-pasted.) Also the prompt
"Xilinx Zynq Quad SPI driver" includes the word "driver"; upstream prefers a short noun phrase

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I've removed select EVENTS from the Kconfig.

Regarding the prompt, I kept 'Xilinx Zynq Quad SPI driver' for now to remain consistent with the existing SPI drivers in the tree (which largely include the word 'driver' in their prompts). However, if you'd prefer me to change it to match the newer style guideline, let me know and I'll update it!

As a side note: I also considered moving the FIFO processing out of the ISR, but left it there to avoid increasing the risk of FIFO overflow/underflow.

Comment thread drivers/spi/spi_xlnx_zynq_qspi.c Outdated
return -ENOTSUP;
}

LOG_DBG("freqency requested=%u input frequency=%u CR_BAUD_RATE_DIV=0x%x actual "

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freqency is misspelled (should be frequency). Also treshholds at line ~566
(/* set FIFO treshholds */, should be thresholds).

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Fixed both typos. Thanks for catching those!

}
#endif /* CONFIG_SPI_ASYNC */

static int zynq_qspi_release(const struct device *dev, const struct spi_config *spi_cfg)

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spi_cfg is unused; missing ARG_UNUSED(spi_cfg);.

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Fixed.

Comment thread drivers/spi/spi_xlnx_zynq_qspi.c Outdated
}
}


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Two consecutive blank lines between functions. remove one

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Fixed.

Comment thread drivers/spi/spi_xlnx_zynq_qspi.c Outdated
@@ -0,0 +1,614 @@
/*
* Copyright (c) 2024 Simon Maurer <mail@maurer.systems>

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2026

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Fixed.

kedareswararao
kedareswararao previously approved these changes Jul 20, 2026

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Changes looks fine to me

@mausys

mausys commented Jul 20, 2026

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fixed a problem in the ISR (remainder was left in the FIFO)

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This pull request has been marked as stale because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 7 days. Note that if it gets closed, you can ask someone to reopen it for you if you do not have the permissions to do so.

@github-actions github-actions Bot added the Stale label Aug 20, 2026
@mausys

mausys commented Aug 21, 2026

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Hi everyone, just wanted to provide a gentle ping on this PR. Let me know if there's anything I can do to help move it forward or if you are waiting on any changes!

@kedareswararao

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@mausys I have removed the stale lable please take a look into the CI failures if it's not releated your changes please rebase changes on top of latest main so that CI checks will re triggered

Add a driver for the Xilinx Zynq 7000 Quad SPI controller. Note that
while the hardware supports legacy SPI, this driver only supports
flash mode.

Signed-off-by: Simon Maurer <mail@maurer.systems>
@zephyrbot

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@venodela

You have been identified as a likely reviewer for the code this pull request changes, but could not be added to its review request automatically. Please review it if you are able to.

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