Refactor nordic socs/drivers to remove GPD and decouple pin retention. #90754

bjarki-andreasen · 2025-05-28T15:18:35Z

Replace highly coupled use of GPD (gpd.h) from device drivers, with power domain device drivers using zephyr's PM_DEVICE_POWER_DOMAIN infrastructure.

The gpd.h currently is used for two things:

Manually requests power domains like fast_active_main and slow_active_main on the H20
Manually applies pin state retention on individual pins, or pins found in a pinctrl config.

Nordic device drivers currently have to do this manually, conditionally, which is adding immense complexity to them, only relevant for certain SoCs, and which is in theory duplicate code. In reality, device drivers do their best, but since gpd is not well understood, device drivers implement it slightly differently, in some cases working by design, some cases working by accident, and in some cases working, but breaking something else.

No more!

Both pin retention and power domains are actually designed in a way that is entirely logical, and can be expressed using power domains and the devicetree. So, using pinctrl and power domains, we can entirely decouple devices from this complexity :)

What does the refactor do?

Rework the nrfh54h power domains to match zephyr's power domains. This means every power domain is represented as a node, not an index in a phandle. This does two things, it allows us to use zephyr's power domain framework, and it stops our misuse of the base power-domains property from breaking user's applications if they "dare" to use zephyrs power domain framework. See first commit.
Introduce the gpio pads to the devicetree. GPIO pads are the SoCs pins, which peripherals like UARTE or GPIO can be muxed to. These can be in different power domains than the peripheral connected to them, and they need to be retained if the power domain they are in may be shut down, which only happens if no peripheral, including GPIO, is active while muxed to any pad in that pad group (a pad group is 1-1 mapped to the GPIO controller, so GPIO0 will own pad group 0). See second commit.
Refactor pinctrl and device drivers to use the new power domains, and remove all usage of gpd.h
Remove gpd.h
Success

drivers/power_domain/power_domain_nrfs_gdpwr.c

karstenkoenig

Didn't look at SWEXT changes, but the gpio port/pad power domain handling looks good.

Will this trigger more power domain requests/releases?

drivers/serial/uart_nrfx_uarte.c

bjarki-andreasen · 2025-07-25T10:39:24Z

Rebased to solve merge conflict

bjarki-andreasen · 2025-07-25T10:39:43Z

ping @anangl @nika-nordic

bjarki-andreasen · 2025-07-28T11:31:38Z

Rebased to include cross domain changes for SPI and UARTE

bjarki-andreasen · 2025-07-28T11:45:04Z

ping @anangl

Introduce the NRFS GDPWR (Global Domain Power Request) device driver and devicetree binding. Signed-off-by: Bjarki Arge Andreasen <[email protected]>

anangl · 2025-07-29T06:04:22Z

dts/bindings/gpio/nordic,nrf-gpio-pad-group.yaml

-  controller which manages the the pad group,
-  named pad-group. The pad group's nodelabel is
-  named gpio_pad_group<GPIO number>.
+  controller which manages the pad group, named
+  pad-group. The pad group's nodelabel is named
+  gpio_pad_group<GPIO number>.


This correction should be done directly in the commit that introduces the binding.

anangl · 2025-07-29T06:08:14Z

dts/vendor/nordic/nrf54h20.dtsi

 			open-loop-startup-time-us = <200>; /* To be measured */
 			clocks = <&hfxo>, <&lfxo>;
 			clock-names = "hfxo", "lfxo";
+			status = "disabled";


nit: it would be probably better to have this right after compatible, like in most of the other nodes here

anangl · 2025-07-29T06:12:58Z

soc/nordic/common/pinctrl_soc.h

+ *
+ * @param pincfg Pin configuration bit field.
+ */
+#define NRF_GET_PORT_PIN(pincfg) (NRF_GET_PORT(pincfg) % 32)


Suggested change

#define NRF_GET_PORT_PIN(pincfg) (NRF_GET_PORT(pincfg) % 32)

#define NRF_GET_PORT_PIN(pincfg) (NRF_GET_PIN(pincfg) & 0x1F)

anangl · 2025-07-29T06:17:47Z

soc/nordic/common/soc_nrf_common.h

+		(										\
+			IS_EQ(									\
+				DT_DEP_ORD(DT_PHANDLE(node_id, power_domains)),			\
+				DT_DEP_ORD(DT_NODELABEL(gdpwr_fast_active_1))			\
+			)									\
+		),										\


Suggested change

( \

IS_EQ( \

DT_DEP_ORD(DT_PHANDLE(node_id, power_domains)), \

DT_DEP_ORD(DT_NODELABEL(gdpwr_fast_active_1)) \

) \

), \

(DT_SAME_NODE(DT_PHANDLE(node_id, power_domains), \

DT_NODELABEL(gdpwr_fast_active_1))), \

This does not work, DT_SAME_NODE uses ==, it does not evaluate to 0 or 1 :)

?

zephyr/include/zephyr/devicetree.h

Lines 692 to 693 in 00e217d

#define DT_SAME_NODE(node_id1, node_id2) \

IS_EQ(DT_DEP_ORD(node_id1), DT_DEP_ORD(node_id2))

oh, this was fixed after I made the commit :D ba48d83

anangl · 2025-07-29T06:28:10Z

tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast_spis.overlay

 	compatible = "nordic,nrf-spim";
 	status = "okay";
+	def-char = <0x00>;


Why? It's a SPIM, not SPIS.

Some driver needs def-char to be set, this was an attempt at trying to fix it.

Issue was with SPIS_NODE macro which checked if an instance was FAST to determine if the nodelabel was spix or spisx, this can't be done since we need to know the nodelabel first, to be able to check if its fast or not, changed to just test if the nodelabel exists:

#define SPIS_NODE(idx) \ COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(spis##idx)), (spis##idx), (spi##idx))

anangl · 2025-07-29T06:32:30Z

dts/vendor/nordic/nrf54h20.dtsi

+	swext: swext {
+		compatible = "nordic,nrfs-swext";
+		max-current-ua = <10000>;
+		current-limit-ua = <10000>;
+		zephyr,pm-device-runtime-auto;
+		#power-domain-cells = <0>;
+		status = "disabled";


Is this added intentionally?

No, It should have been removed as I dropped the swext commit :)

anangl · 2025-07-29T06:44:38Z

drivers/spi/spi_nrfx_spim.c

-	CONFIG_SPI_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
 #define SPIM_INIT_PRIORITY(idx) \
-	COND_CODE_1(SPIM_REQUESTS_CLOCK(SPIM(idx)), \
+	COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _), \


Suggested change

COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _), \

COND_CODE_1(INSTANCE_IS_FAST(_, /*empty*/, idx, _), \

Introduce the NRF GPIO Pad Group device driver and binding. The pad group device represents the GPIO pads (pins), contrary to a GPIO controller, which is one of the many devices which can be muxed to pads in the pad group. The pad group belong to a power domain, which is not neccesarily the same power domain as devices being muxed to the pads, like GPIO or UART. If no ACTIVE device is using any of the pads in the pad group, the pad groups power domain may be SUSPENDED. Before the pad groups power domain is SUSPENDED, pad config retention must be enabled to prevent the pads from loosing their state. That's what this device driver manages. Once retained, the pad configs and outputs are locked, even when their power domain is SUSPENDED. Signed-off-by: Bjarki Arge Andreasen <[email protected]>

Transition nrf54h away from the soc specific gpd (global power domain) driver which mixed power domains, pinctrl and gpio pin retention into a non scalable solution, forcing soc specific logic to bleed into nrf drivers. The new solution uses zephyrs PM_DEVICE based power domains to properly model the hardware layout of device and pin power domains, and moves pin retention logic out of drivers into pinctrl and gpio, which are the components which manage pins (pads). Signed-off-by: Bjarki Arge Andreasen <[email protected]>

Remove the deprecated GPD (Global Power Domain) driver. Signed-off-by: Bjarki Arge Andreasen <[email protected]>

sonarqubecloud · 2025-07-29T10:43:39Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

bjarki-andreasen · 2025-07-29T11:11:55Z

ping @masz-nordic

bjarki-andreasen force-pushed the nrfs-swext-pd branch from afa9528 to 87e9f3a Compare June 16, 2025 22:20

karstenkoenig self-requested a review June 18, 2025 06:49

bjarki-andreasen force-pushed the nrfs-swext-pd branch from f737ae0 to 8654ac9 Compare June 18, 2025 10:44

karstenkoenig reviewed Jun 25, 2025

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drivers/power_domain/power_domain_nrfs_gdpwr.c Show resolved Hide resolved

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drivers/serial/uart_nrfx_uarte.c Show resolved Hide resolved

bjarki-andreasen force-pushed the nrfs-swext-pd branch 2 times, most recently from 95015ed to 1de2f64 Compare July 3, 2025 00:30

bjarki-andreasen added the platform: nRF Nordic nRFx label Jul 3, 2025

bjarki-andreasen force-pushed the nrfs-swext-pd branch 12 times, most recently from 3acab47 to 9163316 Compare July 14, 2025 12:49

bjarki-andreasen force-pushed the nrfs-swext-pd branch 2 times, most recently from 126e8cb to 3e4dca4 Compare July 14, 2025 16:00

bjarki-andreasen marked this pull request as ready for review July 14, 2025 17:12

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bjarki-andreasen requested a review from masz-nordic July 28, 2025 11:44

drivers: power_domain: introduce nrfs gdpwr

e38aa70

Introduce the NRFS GDPWR (Global Domain Power Request) device driver and devicetree binding. Signed-off-by: Bjarki Arge Andreasen <[email protected]>

bjarki-andreasen force-pushed the nrfs-swext-pd branch from af1ee21 to 70d5d49 Compare July 28, 2025 13:35

anangl reviewed Jul 29, 2025

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bjarki-andreasen added 2 commits July 29, 2025 11:35

bjarki-andreasen force-pushed the nrfs-swext-pd branch 2 times, most recently from e47f3a6 to 9d6df0d Compare July 29, 2025 10:10

soc: nrf54h: remove deprecated gpd (global power domain) driver

e4f5b0d

Remove the deprecated GPD (Global Power Domain) driver. Signed-off-by: Bjarki Arge Andreasen <[email protected]>

bjarki-andreasen force-pushed the nrfs-swext-pd branch from 9d6df0d to e4f5b0d Compare July 29, 2025 10:12

anangl approved these changes Jul 29, 2025

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masz-nordic approved these changes Jul 29, 2025

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cfriedt merged commit 2854115 into zephyrproject-rtos:main Jul 29, 2025
30 checks passed

carlescufi mentioned this pull request Jul 31, 2025

drivers: serial: nrfx_uarte: Reorder suspend #91550

Closed

jonathannilsen mentioned this pull request Aug 28, 2025

[nrf noup] soc: nrf54h: work around missing power domain handling nrfconnect/sdk-zephyr#3233

Merged

	#define NRF_GET_PORT_PIN(pincfg) (NRF_GET_PORT(pincfg) % 32)
	#define NRF_GET_PORT_PIN(pincfg) (NRF_GET_PIN(pincfg) & 0x1F)

	#define DT_SAME_NODE(node_id1, node_id2) \
	IS_EQ(DT_DEP_ORD(node_id1), DT_DEP_ORD(node_id2))

	COND_CODE_1(INSTANCE_IS_FAST_PD(_, /empty/, idx, _), \
	COND_CODE_1(INSTANCE_IS_FAST(_, /empty/, idx, _), \

Refactor nordic socs/drivers to remove GPD and decouple pin retention. #90754

Refactor nordic socs/drivers to remove GPD and decouple pin retention. #90754

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bjarki-andreasen commented May 28, 2025 •

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