GIPC: Introduce G-stage table In Process Context (GIPC) - #43
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The current G-stage page table of RISC-V IOMMU resides within the device context and is only bound to one DC (G-stage table In Device Context - GIDC). Consequently, this limits the SHWQ (shared hardware work queue) to serve only one virtual machine. The SHWQ uses process_id to distinguish the different address spaces. So, adding iohgatp into Process Context could make SHWQ serve different virtual machines. The GIPC (G-stage table In Process Context) capability [1] adds iohgatp in PC (Process Context), and makes RISC-V IOMMU support GIPC and GIDC simultaneously. This improves the virtualization scalability of heterogeneous programming in shared hardware work queue scenarios [2]. Because RVI hasn't ratified GIPC, this patch uses custom bit fields of dc.tc & capability regs. [1] riscv-non-isa/riscv-iommu#413 [2] https://www.youtube.com/watch?v=-fuqzYedOb0 Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
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The current G-stage page table of RISC-V IOMMU resides within the device context and is only bound to one DC (G-stage table In Device Context - GIDC). Consequently, this limits the SHWQ (shared hardware work queue) to serve only one virtual machine. The SHWQ uses process_id to distinguish the different address spaces. So, adding iohgatp into Process Context could make SHWQ serve different virtual machines.
The GIPC (G-stage table In Process Context) capability [1] adds iohgatp in PC (Process Context), and makes RISC-V IOMMU support GIPC and GIDC simultaneously. This improves the virtualization scalability of heterogeneous programming in shared hardware work queue scenarios [2].
Because RVI hasn't ratified GIPC, this patch uses custom bit fields of dc.tc & capability regs.
[1] riscv-non-isa/riscv-iommu#413
[2] https://www.youtube.com/watch?v=-fuqzYedOb0