Fixing bug found via synthesis

aolofsson · aolofsson · commit 29a4c4c7e31e · 2025-07-01T16:41:52.000-04:00
diff --git a/logikbench/arithmetic/sum/rtl/sum.v b/logikbench/arithmetic/sum/rtl/sum.v
@@ -1,6 +1,6 @@
-module dotprod #(parameter N = 8,  // Number of elements
-                 parameter DW = 16 // Bitwidth of each element
-                 )
+module sum #(parameter N = 8,  // Number of elements
+             parameter DW = 16 // Bitwidth of each element
+             )
    (
     input [N*DW-1:0]             a,  // concatenated input vector a
     input [N*DW-1:0]             b,  // concatenated input vector b
