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1 parent 9399292 commit 4067731Copy full SHA for 4067731
2 files changed
tests/template.ys.j2
tests/test_yosys.py
@@ -1,11 +1,24 @@
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import common
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import subprocess
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-from jinja2 import Environment, FileSystemLoader
+from jinja2 import Template
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def run_yosys(dlist):
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- env = Environment(loader=FileSystemLoader('.'))
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- template = env.get_template('template.ys.j2')
+ yosys_template = """
+# Read the Verilog source file
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+read_verilog_file_list -f {{ cmdfile }}
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+
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+# Set the top module
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+hierarchy -top {{ topmodule }}
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+# Generic synthesis
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+proc; opt; flatten; opt
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+# Write synthesized netlist in Verilog
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+write_verilog {{ netlist }}
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+"""
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+ template = Template(yosys_template)
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for item in dlist:
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name = item.name()
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