Adding more key DSP blocks

Author: aolofsson

logikbench/__init__.py

@@ -83,6 +83,9 @@
 from .blocks.aes.aes import Aes
 from .blocks.axicrossbar.axicrossbar import Axicrossbar
 from .blocks.ethmac.ethmac import Ethmac
+from .blocks.fft.fft import Fft
+from .blocks.firfix.firfix import Firfix
+from .blocks.firprog.firprog import Firprog
 from .blocks.ialu.ialu import Ialu
 from .blocks.i2c.i2c import I2c
 from .blocks.lfsr.lfsr import Lfsr

logikbench/blocks/fft/rtl/fft.v

@@ -38,6 +38,8 @@ module fft
    reg [LOG2N:0]       output_count;
    reg                 processing;
 
+   // static look up table
+   reg signed [DW-1:0] sine_lut [0:255];
 
    integer             i;
 
@@ -144,8 +146,6 @@ module fft
       end
    endfunction
 
-   reg signed [DW-1:0] sine_lut [0:255];
-
    initial
      begin
         sine_lut[0] = 16'sd0;

logikbench/blocks/firfix/firfix.py

@@ -2,7 +2,7 @@
 from siliconcompiler.design import DesignSchema
 
 
-class Fir(DesignSchema):
+class Firfix(DesignSchema):
     def __init__(self):
 
         name = 'firfix'

logikbench/blocks/firprog/firprog.py

@@ -2,7 +2,7 @@
 from siliconcompiler.design import DesignSchema
 
 
-class Fir(DesignSchema):
+class Firprog(DesignSchema):
     def __init__(self):
 
         name = 'firprog'

logikbench/blocks/firprog/rtl/firprog.v

@@ -1,6 +1,6 @@
 /****************************************************************************
  *  LICENSE: MIT (see ../../../../LICENSE)
- *  AUTHOR: LogikBench authors
+ *  AUTHOR: LogikBench Authors
  ****************************************************************************
  *  DESCRIPTION:
  *

tests/common.py

@@ -74,6 +74,8 @@
 block_list = [Aes(),
               Axicrossbar(),
               Ethmac(),
+              Firfix(),
+              Firprog(),
               Ialu(),
               I2c(),
               Lfsr(),