Removing redundant comments

aolofsson · aolofsson · commit 459bdcc34989 · 2025-07-12T08:31:58.000-04:00
diff --git a/logikbench/basic/arbiter/rtl/arbiter.v b/logikbench/basic/arbiter/rtl/arbiter.v
@@ -1,4 +1,4 @@
-module arbiter #(parameter N = 8)
+module arbiter #(parameter N = 16)
    (
     input [N-1:0]      request, // request inputs, [0] is highest priority
     output reg [N-1:0] grant    // one hot grant vector
diff --git a/logikbench/basic/band/rtl/band.v b/logikbench/basic/band/rtl/band.v
@@ -1,4 +1,4 @@
-module band #(parameter DW = 32 // data width
+module band #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/bbuf/rtl/bbuf.v b/logikbench/basic/bbuf/rtl/bbuf.v
@@ -1,4 +1,4 @@
-module bbuf #(parameter DW = 32 // data width
+module bbuf #(parameter DW = 64
               )
    (
     input [DW-1:0]  in,
diff --git a/logikbench/basic/bin2gray/rtl/bin2gray.v b/logikbench/basic/bin2gray/rtl/bin2gray.v
@@ -1,4 +1,4 @@
-module bin2gray #(parameter DW = 32 // data width
+module bin2gray #(parameter DW = 64
                   )
    (
     input [DW-1:0]  in, // binary input
diff --git a/logikbench/basic/bin2prio/rtl/bin2prio.v b/logikbench/basic/bin2prio/rtl/bin2prio.v
@@ -1,4 +1,4 @@
-module bin2prio #(parameter DW = 32) // data width
+module bin2prio #(parameter DW = 64)
    (
     input [DW-1:0]      in,   // binary input vector
     output reg [DW-1:0] out,  // one hot output
diff --git a/logikbench/basic/binv/rtl/binv.v b/logikbench/basic/binv/rtl/binv.v
@@ -1,4 +1,4 @@
-module binv #(parameter DW = 32 // data width
+module binv #(parameter DW = 64
               )
    (
     input [DW-1:0]  in,
diff --git a/logikbench/basic/bnand/rtl/bnand.v b/logikbench/basic/bnand/rtl/bnand.v
@@ -1,4 +1,4 @@
-module bnand #(parameter DW = 32 // data width
+module bnand #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/bnor/rtl/bnor.v b/logikbench/basic/bnor/rtl/bnor.v
@@ -1,4 +1,4 @@
-module bnor #(parameter DW = 32 // data width
+module bnor #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/bor/rtl/bor.v b/logikbench/basic/bor/rtl/bor.v
@@ -1,4 +1,4 @@
-module bor #(parameter DW = 32 // data width
+module bor #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/bxnor/rtl/bxnor.v b/logikbench/basic/bxnor/rtl/bxnor.v
@@ -1,4 +1,4 @@
-module bxnor #(parameter DW = 32 // data width
+module bxnor #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/bxor/rtl/bxor.v b/logikbench/basic/bxor/rtl/bxor.v
@@ -1,4 +1,4 @@
-module bxor #(parameter DW = 32 // data width
+module bxor #(parameter DW = 64
               )
    (
     input [DW-1:0] in,
diff --git a/logikbench/basic/crossbar/rtl/crossbar.v b/logikbench/basic/crossbar/rtl/crossbar.v
@@ -1,5 +1,5 @@
-module crossbar #(parameter DW = 16, // data width
-                  parameter N = 8    // number of ports
+module crossbar #(parameter DW = 64,
+                  parameter N = 16   // number of ports
                   )
    (
     input [N*DW-1:0]      din, // N DW-wide input words, concatenated
diff --git a/logikbench/basic/dffasync/rtl/dffasync.v b/logikbench/basic/dffasync/rtl/dffasync.v
@@ -1,4 +1,4 @@
-module dffasync #(parameter DW = 16
+module dffasync #(parameter DW = 64
                   )
    (
     input               clk,
diff --git a/logikbench/basic/dffsync/rtl/dffsync.v b/logikbench/basic/dffsync/rtl/dffsync.v
@@ -1,4 +1,4 @@
-module dffsync #(parameter DW = 16
+module dffsync #(parameter DW = 64
                  )
    (
     input               clk,
diff --git a/logikbench/basic/gray2bin/rtl/gray2bin.v b/logikbench/basic/gray2bin/rtl/gray2bin.v
@@ -1,4 +1,4 @@
-module gray2bin #(parameter DW = 32) // data width
+module gray2bin #(parameter DW = 64)
    (
     input [DW-1:0]  in, // gray encoded input
     output [DW-1:0] out // binary output
diff --git a/logikbench/basic/mux/rtl/mux.v b/logikbench/basic/mux/rtl/mux.v
@@ -1,5 +1,5 @@
-module mux #(parameter DW = 16, // data width
-             parameter N = 8    // number of inputs (power of 2)
+module mux #(parameter DW = 64,
+             parameter N = 16   // number of inputs (power of 2)
              )
    (
     input [$clog2(N)-1:0] sel,  // binary select signal
diff --git a/logikbench/basic/muxcase/rtl/muxcase.v b/logikbench/basic/muxcase/rtl/muxcase.v
@@ -1,4 +1,4 @@
-module muxcase #(parameter DW = 8 // data width
+module muxcase #(parameter DW = 64
                  )
    (
     input [7:0]         sel, // binary select signal
diff --git a/logikbench/basic/muxhot/rtl/muxhot.v b/logikbench/basic/muxhot/rtl/muxhot.v
@@ -1,5 +1,5 @@
-module muxhot #(parameter DW = 8, // data width
-                parameter N = 8   // number of vectors
+module muxhot #(parameter DW = 64,
+                parameter N = 16 // number of inputs
                 )
    (
     input [N-1:0]    sel, // select vector
diff --git a/logikbench/basic/muxpri/rtl/muxpri.v b/logikbench/basic/muxpri/rtl/muxpri.v
@@ -1,5 +1,5 @@
-module muxpri #(parameter DW = 32, // data width
-                parameter N = 2    // number of inputs (power of 2)
+module muxpri #(parameter DW = 64,
+                parameter N = 2    // number of inputs
                 )
    (
     input [N-1:0]       sel,  // select signals
diff --git a/logikbench/basic/onehot/rtl/onehot.v b/logikbench/basic/onehot/rtl/onehot.v
@@ -1,4 +1,4 @@
-module onehot #(parameter DW = 32 // must be power of 2!
+module onehot #(parameter DW = 64 // must be power of 2
                 )
    (
     input wire [$clog2(DW)-1:0] in, // binary input
diff --git a/logikbench/basic/pipeline/rtl/pipeline.v b/logikbench/basic/pipeline/rtl/pipeline.v
@@ -1,5 +1,5 @@
-module pipeline #(parameter DW = 32, // data width
-                  parameter N = 8    // pipeline stages
+module pipeline #(parameter DW = 64,
+                  parameter N = 16   // pipeline stages
                   )
    (
     input           clk,
diff --git a/logikbench/basic/shiftreg/rtl/shiftreg.v b/logikbench/basic/shiftreg/rtl/shiftreg.v
@@ -1,4 +1,4 @@
-module shiftreg # (parameter DW = 8
+module shiftreg # (parameter DW = 64
                    )
    (
     input           clk,

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module arbiter #(parameter N = 8)`
	`1`	`+module arbiter #(parameter N = 16)`
`2`	`2`	`(`
`3`	`3`	`input [N-1:0] request, // request inputs, [0] is highest priority`
`4`	`4`	`output reg [N-1:0] grant // one hot grant vector`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module band #(parameter DW = 32 // data width`
	`1`	`+module band #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bbuf #(parameter DW = 32 // data width`
	`1`	`+module bbuf #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bin2gray #(parameter DW = 32 // data width`
	`1`	`+module bin2gray #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in, // binary input`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bin2prio #(parameter DW = 32) // data width`
	`1`	`+module bin2prio #(parameter DW = 64)`
`2`	`2`	`(`
`3`	`3`	`input [DW-1:0] in, // binary input vector`
`4`	`4`	`output reg [DW-1:0] out, // one hot output`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module binv #(parameter DW = 32 // data width`
	`1`	`+module binv #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bnand #(parameter DW = 32 // data width`
	`1`	`+module bnand #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bnor #(parameter DW = 32 // data width`
	`1`	`+module bnor #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bor #(parameter DW = 32 // data width`
	`1`	`+module bor #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module bxnor #(parameter DW = 32 // data width`
	`1`	`+module bxnor #(parameter DW = 64`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input [DW-1:0] in,`