Fixing default parameters to be consistent for arithmetic benchmarks

aolofsson · aolofsson · commit 800470a1691c · 2025-07-12T08:27:02.000-04:00
- Can always be overridden at runtime.
diff --git a/logikbench/arithmetic/abs/rtl/abs.v b/logikbench/arithmetic/abs/rtl/abs.v
@@ -1,4 +1,4 @@
-module abs #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module abs #(parameter DW = 16
 	     )
    (
     //Inputs
diff --git a/logikbench/arithmetic/absdiff/rtl/absdiff.v b/logikbench/arithmetic/absdiff/rtl/absdiff.v
@@ -1,4 +1,4 @@
-module absdiff #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module absdiff #(parameter DW = 16
 	         )
    (
     //Inputs
diff --git a/logikbench/arithmetic/absdiffs/rtl/absdiffs.v b/logikbench/arithmetic/absdiffs/rtl/absdiffs.v
@@ -1,4 +1,4 @@
-module absdiffs #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module absdiffs #(parameter DW = 16
 	         )
    (
     //Inputs
diff --git a/logikbench/arithmetic/add/rtl/add.v b/logikbench/arithmetic/add/rtl/add.v
@@ -1,15 +1,15 @@
-module add #(parameter N = 8  // Operator width (8,16,32,64,128,...)
+module add #(parameter DW = 16
 	     )
    (
     //Inputs
-    input [N-1:0]  a,
-    input [N-1:0]  b,
-    input          cin,
+    input [DW-1:0]  a,
+    input [DW-1:0]  b,
+    input           cin,
     //Outputs
-    output         cout,
-    output [N-1:0] z
+    output          cout,
+    output [DW-1:0] z
     );
 
-   assign {cout, z[N-1:0]} = a[N-1:0] + b[N-1:0] + cin;
+   assign {cout, z} = a + b + cin;
 
 endmodule
diff --git a/logikbench/arithmetic/addsub/rtl/addsub.v b/logikbench/arithmetic/addsub/rtl/addsub.v
@@ -1,12 +1,12 @@
-module addsub #(parameter N = 8  // Operator width (8,16,32,64,128,...)
+module addsub #(parameter DW = 16
 	     )
    (
     //Inputs
-    input [N-1:0]  a,
-    input [N-1:0]  b,
-    input          sel,
+    input [DW-1:0]  a,
+    input [DW-1:0]  b,
+    input           sel,
     //Outputs
-    output [N-1:0] z
+    output [DW-1:0] z
     );
 
    assign z = sel ? a + b : a - b;
diff --git a/logikbench/arithmetic/cmp/rtl/cmp.v b/logikbench/arithmetic/cmp/rtl/cmp.v
@@ -1,5 +1,5 @@
-module cmp #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
-	         )
+module cmp #(parameter DW = 16
+	     )
    (
     //Inputs
     input [DW-1:0] a,
diff --git a/logikbench/arithmetic/counter/rtl/counter.v b/logikbench/arithmetic/counter/rtl/counter.v
@@ -1,4 +1,4 @@
-module counter #(parameter DW = 16  // counter width
+module counter #(parameter DW = 16
              )
    (
     input               clk,
diff --git a/logikbench/arithmetic/csa32/rtl/csa32.v b/logikbench/arithmetic/csa32/rtl/csa32.v
@@ -1,4 +1,4 @@
-module csa32 #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module csa32 #(parameter DW = 16
 	       )
    (
     //Inputs
diff --git a/logikbench/arithmetic/csa42/rtl/csa42.v b/logikbench/arithmetic/csa42/rtl/csa42.v
@@ -1,4 +1,4 @@
-module csa42 #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module csa42 #(parameter DW = 16
 	       )
    (input [DW-1:0]  in0,  // input
     input [DW-1:0]  in1,  // input
diff --git a/logikbench/arithmetic/dec/rtl/dec.v b/logikbench/arithmetic/dec/rtl/dec.v
@@ -1,9 +1,9 @@
-module dec #(parameter N = 8  // Operator width (8,16,32,64,128,...)
+module dec #(parameter DW = 16
 	     )
    (
     //Inputs
-    input [N-1:0]  a,
-    output [N-1:0] z
+    input [DW-1:0]  a,
+    output [DW-1:0] z
     );
 
    assign z = a - 1'b1;
diff --git a/logikbench/arithmetic/dotprod/rtl/dotprod.v b/logikbench/arithmetic/dotprod/rtl/dotprod.v
@@ -1,5 +1,5 @@
-module dotprod #(parameter N = 8,  // Number of elements
-                 parameter DW = 16 // Bitwidth of each element
+module dotprod #(parameter N = 8,
+                 parameter DW = 16
                  )
    (
     input [N*DW-1:0]             a,  // concatenated input vector a
diff --git a/logikbench/arithmetic/inc/rtl/inc.v b/logikbench/arithmetic/inc/rtl/inc.v
@@ -1,9 +1,10 @@
-module inc #(parameter N = 8  // Operator width (8,16,32,64,128,...)
+module inc #(parameter DW = 16
+
 	     )
    (
     //Inputs
-    input [N-1:0]  a,
-    output [N-1:0] z
+    input [DW-1:0]  a,
+    output [DW-1:0] z
     );
 
    assign z = a + 1'b1;
diff --git a/logikbench/arithmetic/log2/rtl/log2.v b/logikbench/arithmetic/log2/rtl/log2.v
@@ -1,4 +1,4 @@
-module log2 #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module log2 #(parameter DW = 16
 	      )
    (
     input [DW-1:0]            in,
diff --git a/logikbench/arithmetic/mac/rtl/mac.v b/logikbench/arithmetic/mac/rtl/mac.v
@@ -1,13 +1,13 @@
-module mac #(parameter DW = 16,  // input data widths
-             parameter ACCW = 40 // accumulator width
+module mac #(parameter DW = 16,
+             parameter OW = 40
              )
    (
-    input                 clk,
-    input                 clear,
-    input                 en,
-    input [DW-1:0]        a,
-    input [DW-1:0]        b,
-    output reg [ACCW-1:0] acc
+    input               clk,
+    input               clear,
+    input               en,
+    input [DW-1:0]      a,
+    input [DW-1:0]      b,
+    output reg [OW-1:0] acc
     );
 
    always @(posedge clk) begin
diff --git a/logikbench/arithmetic/max/rtl/max.v b/logikbench/arithmetic/max/rtl/max.v
@@ -1,5 +1,5 @@
-module max #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
-	         )
+module max #(parameter DW = 16
+	     )
    (
     //Inputs
     input [DW-1:0]  a,
diff --git a/logikbench/arithmetic/min/rtl/min.v b/logikbench/arithmetic/min/rtl/min.v
@@ -1,4 +1,4 @@
-module min #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module min #(parameter DW = 16
 	         )
    (
     //Inputs
diff --git a/logikbench/arithmetic/mul/rtl/mul.v b/logikbench/arithmetic/mul/rtl/mul.v
@@ -1,14 +1,14 @@
-module mul #(parameter N = 8, // input width
-             parameter M = 8  // output width(>=N)
+module mul #(parameter DW = 16,
+             parameter OW = 32
 	     )
    (
     //Inputs
-    input [N-1:0]  a, // a input (multiplier)
-    input [N-1:0]  b, // b input (multiplicand)
+    input [DW-1:0]  a, // a input (multiplier)
+    input [DW-1:0]  b, // b input (multiplicand)
     //Outputs
-    output [M-1:0] c  // a * b final product
+    output [OW-1:0] c  // a * b final product
     );
 
-   assign c[M-1:0] = a[N-1:0] * b[N-1:0];
+   assign c[DW-1:0] = a[DW-1:0] * b[DW-1:0];
 
 endmodule
diff --git a/logikbench/arithmetic/muladd/rtl/muladd.v b/logikbench/arithmetic/muladd/rtl/muladd.v
@@ -1,15 +1,15 @@
-module muladd #(parameter N = 8, // input width
-                parameter M = 8 // output width (>=N)
+module muladd #(parameter DW = 16,
+                parameter OW = 32,
 	        )
    (
     //Inputs
-    input [N-1:0]  a, // a input (multiplier)
-    input [N-1:0]  b, // b input (multiplicand)
-    input [M-1:0]  c, // c input (add input)
+    input [DW-1:0]  a, // a input (multiplier)
+    input [DW-1:0]  b, // b input (multiplicand)
+    input [OW-1:0]  c, // c input (add input)
     //Outputs
-    output [M-1:0] z  // a * b + c
+    output [OW-1:0] z  // a * b + c
     );
 
-   assign z[M-1:0] = a[N-1:0] * b[N-1:0] + c[M-1:0];
+   assign z = a * b + c;
 
 endmodule
diff --git a/logikbench/arithmetic/muladdc/rtl/muladdc.v b/logikbench/arithmetic/muladdc/rtl/muladdc.v
@@ -1,15 +1,15 @@
-module muladdc #(parameter DW = 16,  // width of RE and IM inputs
-                 parameter ACCW = 40 // accumulator width
+module muladdc #(parameter DW = 16,
+                 parameter OW = 40
                  )
    (
-    input signed [DW-1:0]    a_re,
-    input signed [DW-1:0]    a_im,
-    input signed [DW-1:0]    b_re,
-    input signed [DW-1:0]    b_im,
-    input signed [ACCW-1:0]  c_re,
-    input signed [ACCW-1:0]  c_im,
-    output signed [ACCW-1:0] out_re,
-    output signed [ACCW-1:0] out_im
+    input signed [DW-1:0]  a_re,
+    input signed [DW-1:0]  a_im,
+    input signed [DW-1:0]  b_re,
+    input signed [DW-1:0]  b_im,
+    input signed [OW-1:0]  c_re,
+    input signed [OW-1:0]  c_im,
+    output signed [OW-1:0] out_re,
+    output signed [OW-1:0] out_im
     );
 
    wire [2*DW-1:0] prod_re;
diff --git a/logikbench/arithmetic/mulc/rtl/mulc.v b/logikbench/arithmetic/mulc/rtl/mulc.v
@@ -1,4 +1,4 @@
-module mulc #(parameter DW = 16 // width of RE and IM inputs
+module mulc #(parameter DW = 16
               )
    (
     input signed [DW-1:0]    a_re,
diff --git a/logikbench/arithmetic/mulreg/rtl/mulreg.v b/logikbench/arithmetic/mulreg/rtl/mulreg.v
@@ -1,31 +1,31 @@
-module mulreg #(parameter N = 8, // input width
-                parameter M = 8  // output width(>=N)
+module mulreg #(parameter DW = 16,
+                parameter OW = 32
 	        )
    (
     //Inputs
-    input                     clk, // clock
-    input signed [N-1:0]      a,   // a input (multiplier)
-    input signed [N-1:0]      b,   // b input (multiplicand)
+    input                      clk, // clock
+    input signed [DW-1:0]      a,   // a input (multiplier)
+    input signed [DW-1:0]      b,   // b input (multiplicand)
     //Outputs
-    output reg signed [M-1:0] out  // a * b
+    output reg signed [OW-1:0] out  // a * b
     );
 
-   reg signed [N-1:0] areg;
-   reg signed [N-1:0] breg;
-   wire signed [M-1:0] prod;
+   reg signed [DW-1:0] areg;
+   reg signed [DW-1:0] breg;
+   wire signed [OW-1:0] prod;
 
    // register inputs
    always @ (posedge clk)
      begin
-        areg[N-1:0] <= a;
-        breg[N-1:0] <= b;
+        areg[DW-1:0] <= a;
+        breg[DW-1:0] <= b;
      end
 
    // multiplier
-   assign prod[M-1:0] = areg[N-1:0] * breg[N-1:0];
+   assign prod[OW-1:0] = areg[DW-1:0] * breg[DW-1:0];
 
    // register output
    always @ (posedge clk)
-     out[M-1:0]  <= prod;
+     out[OW-1:0]  <= prod;
 
 endmodule
diff --git a/logikbench/arithmetic/muls/rtl/muls.v b/logikbench/arithmetic/muls/rtl/muls.v
@@ -1,14 +1,14 @@
-module muls #(parameter N = 8, // input width
-              parameter M = 8  // output width (>=N)
+module muls #(parameter DW = 16,
+              parameter OW = 32
 	      )
    (
     //Inputs
-    input signed [N-1:0]  a, // a input (multiplier)
-    input signed [N-1:0]  b, // b input (multiplicand)
+    input signed [DW-1:0]  a, // a input (multiplier)
+    input signed [DW-1:0]  b, // b input (multiplicand)
     //Outputs
-    output signed [M-1:0] c  // a * b final product
+    output signed [OW-1:0] c  // a * b final product
     );
 
-   assign c[M-1:0] = a[N-1:0] * b[N-1:0];
+   assign c[OW-1:0] = a[DW-1:0] * b[DW-1:0];
 
 endmodule
diff --git a/logikbench/arithmetic/relu/rtl/relu.v b/logikbench/arithmetic/relu/rtl/relu.v
@@ -1,7 +1,7 @@
-module relu #(parameter N = 8) // data width
+module relu #(parameter DW = 16)
    (
-    input signed [N-1:0]  in,
-    output signed [N-1:0] out
+    input signed [DW-1:0]  in,
+    output signed [DW-1:0] out
     );
 
    assign out = (in > 0) ? in : 0;
diff --git a/logikbench/arithmetic/round/rtl/round.v b/logikbench/arithmetic/round/rtl/round.v
@@ -1,5 +1,5 @@
-module round #(parameter DW = 8, // data width
-               parameter FW = 4  // frection width (<DW)
+module round #(parameter DW = 16,
+               parameter FW = 8 // frection width (<DW)
                )
    (
     //Inputs
diff --git a/logikbench/arithmetic/shiftar/rtl/shiftar.v b/logikbench/arithmetic/shiftar/rtl/shiftar.v
@@ -1,4 +1,4 @@
-module shiftar #(parameter DW = 32
+module shiftar #(parameter DW = 16
 	       )
    (
     //Inputs
diff --git a/logikbench/arithmetic/shiftb/rtl/shiftb.v b/logikbench/arithmetic/shiftb/rtl/shiftb.v
@@ -1,4 +1,4 @@
-module shiftb #(parameter DW = 32  // Data width
+module shiftb #(parameter DW = 16
                 )
    (
     input [DW-1:0]         a,     // Input data
diff --git a/logikbench/arithmetic/shiftl/rtl/shiftl.v b/logikbench/arithmetic/shiftl/rtl/shiftl.v
@@ -1,4 +1,4 @@
-module shiftl #(parameter DW = 32
+module shiftl #(parameter DW = 16
 	       )
    (
     //Inputs
diff --git a/logikbench/arithmetic/shiftr/rtl/shiftr.v b/logikbench/arithmetic/shiftr/rtl/shiftr.v
@@ -1,4 +1,4 @@
-module shiftr #(parameter DW = 32
+module shiftr #(parameter DW = 16
 	       )
    (
     //Inputs
diff --git a/logikbench/arithmetic/sqdiff/rtl/sqdiff.v b/logikbench/arithmetic/sqdiff/rtl/sqdiff.v
@@ -1,4 +1,4 @@
-module sqdiff #(parameter DW = 8  // Operator width (8,16,32,64,128,...)
+module sqdiff #(parameter DW = 16
 	        )
    (
     //Inputs
diff --git a/logikbench/arithmetic/sub/rtl/sub.v b/logikbench/arithmetic/sub/rtl/sub.v
@@ -1,13 +1,13 @@
-module sub #(parameter N = 8  // Operator width (8,16,32,64,128,...)
+module sub #(parameter DW = 16
 	     )
    (
     //Inputs
-    input [N-1:0]  a,
-    input [N-1:0]  b,
+    input [DW-1:0]  a,
+    input [DW-1:0]  b,
     //Outputs
-    output [N-1:0] z
+    output [DW-1:0] z
     );
 
-   assign {cout, z[N-1:0]} = a[N-1:0] - b[N-1:0];
+   assign {cout, z[DW-1:0]} = a[DW-1:0] - b[DW-1:0];
 
 endmodule
diff --git a/logikbench/arithmetic/sum/rtl/sum.v b/logikbench/arithmetic/sum/rtl/sum.v
@@ -1,5 +1,5 @@
-module sum #(parameter N = 8,  // Number of elements
-             parameter DW = 16 // Bitwidth of each element
+module sum #(parameter N = 8,
+             parameter DW = 16
              )
    (
     input [N*DW-1:0]             a,  // concatenated input vector a

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module abs #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module abs #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module absdiff #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module absdiff #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module absdiffs #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module absdiffs #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`		`-module cmp #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
`2`		`- )`
	`1`	`+module cmp #(parameter DW = 16`
	`2`	`+ )`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
`5`	`5`	`input [DW-1:0] a,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module counter #(parameter DW = 16 // counter width`
	`1`	`+module counter #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`input clk,`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module csa32 #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module csa32 #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-module csa42 #(parameter DW = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module csa42 #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(input [DW-1:0] in0, // input`
`4`	`4`	`input [DW-1:0] in1, // input`
Original file line number	Diff line number	Diff line change
`@@ -1,9 +1,9 @@`
`1`		`-module dec #(parameter N = 8 // Operator width (8,16,32,64,128,...)`
	`1`	`+module dec #(parameter DW = 16`
`2`	`2`	`)`
`3`	`3`	`(`
`4`	`4`	`//Inputs`
`5`		`- input [N-1:0] a,`
`6`		`- output [N-1:0] z`
	`5`	`+ input [DW-1:0] a,`
	`6`	`+ output [DW-1:0] z`
`7`	`7`	`);`
`8`	`8`
`9`	`9`	`assign z = a - 1'b1;`