CheriFreeRTOS hmka2 merge #416
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TCP/IP stack + HTTP server + Echo clients/servers. It can build in cheribuild, but to run it, it needs a tap interface. Example command (for refernce): qemu-system-riscv64cheri -M virt -m 2048 -nographic -bios ./RISC-V-Generic_main_peekpoke.elf \ -device virtio-net-device,netdev=net0,mac=00:0a:35:04:db:77 -netdev \ tap,id=net0,ifname=tap0,script=no,downscript=no
This include HTTP, Echo, CLI, FTP, TFTP servers and FAT file system
Basing all FreeRTOS repos on the new official FreeRTOS GitHub repo forks, 202012-LTS release Only RISC-V-Generic is added, Galois' demos aren't included (yet).
Let FreeRTOS build system fails instead if the demo in not supported. This reduces maintenace effort having to add new demos in cheribuild
…ructions support)
CheriFreeRTOS/libdl sets up global sym table for FreeRTOS, libc, and compiler-rt symbols and dynamically link against that lazily if a module references it. Hidden visibiliy makes all compiler-rt local/hidden and not be part of the global sym table which fails dynamic linking/loading.
Only works for libs to be linked with CheriFreeRTOS such as newlib and compiler-rt
…rectory This it to avoid having to rebuild compiler-rt every time another project with another ABI is rebuilt.
Needed for the existing compiler-rt-baremetal-riscv32-hybrid target.
Picocom misses some output when the serial output is too fast with lots of characters
) Many RISC-V simulators start with memory implicitly zeroed. I have PR-d a commit to CTSRD-CHERI/FreeRTOS-Demos-CHERI-RISC-V#5 which allows the .bss and .sbss zero-initialization to be disabled in these cases, because it takes too long to simulate and isn't necessary in this case. This commit adds an option to cheribuild which passes an option to the FreeRTOS demos to disable the zero-initialization.
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pycheribuild/config/chericonfig.py
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| self.riscv_baremetal_hardfloat = loader.add_bool_option("riscv-baremetal-hardfloat", default=False, | ||
| group=loader.cross_compile_options_group, | ||
| help="Use hard floating point ABI for building CHERI-RISC-V programs") | ||
| self.riscv_cheri_rvc = loader.add_bool_option("riscv-cheri-rvc", default=False, |
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C is the default behaviour, do you need this diff?
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@arichardson Not anymore, I added this option when it wasn't the default. I have deleted this diff now.
* Comply with new typing for QEMU targets * Add xlen for 32-bit builds * Don't use gprel branch in LLVM by default, it's only needed for compartmentalisation * Remove vcu118-baremetal * Uncomment Alex's notifications in Jenkinsfile * Remove RISC-V's RVC option as it is now enabled by default
FreeRTOS only runs in M-Mode with the -bios flag without a kernel nor a disk image (typically).
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This is a first cut at trying to merge my old CheriFreeRTOS hmka2 branches into main so that others can use it with the latest toolchain, and validate/build on top of it. It could also be useful for CI to build, run, and test something quick (e.g., with toolchain updates, QEMU, or FPGA), and for other parties wanting to submit fixes or features on top of our CheriFreeRTOS.
It should be able to build and run vanilla RISC-V FreeRTOS and purecap CheriFreeRTOS on many targets, with lots of demos, ranging from simple
main_blinkythat only prints a few messages, to full OTA demos and CLI using networking, VirtIO, ethernet, etc. This merge will lack support for compartmentalisation, however, as it requires a specificgprelLLVM branch. I leftgprelconditional there in case someone might want to still use it.