CheriFreeRTOS hmka2 merge

pycheribuild/config/chericonfig.py

@@ -328,6 +328,14 @@ def __init__(self, loader, action_class: "type[CheribuildActionEnum]") -> None:
             group=loader.cross_compile_options_group,
             help="The floating point/SIMD mode to use for building AArch64 programs",
         )
+
+        self.riscv_baremetal_hardfloat = loader.add_bool_option("riscv-baremetal-hardfloat", default=False,
+            group=loader.cross_compile_options_group,
+            help="Use hard floating point ABI for building CHERI-RISC-V programs")
+        self.riscv_cheri_gprel = loader.add_bool_option("riscv-cheri-gprel", default=False,
+            group=loader.cross_compile_options_group,
+            help="Build CHERI-RISC-V libs with gprel ABI for CheriFreeRTOS compartmentalization")
+
         self.crosscompile_linkage = loader.add_option(
             "cross-compile-linkage",
             default=Linkage.DEFAULT,

pycheribuild/config/compilation_targets.py

@@ -277,9 +277,16 @@ def essential_compiler_and_linker_flags_impl(
             result.append("-mabi=" + cls.get_riscv_abi(xtarget, softfloat=softfloat))
             result.append("-mrelax" if _linker_supports_riscv_relaxations(instance.linker, config) else "-mno-relax")
 
+            softfloat = not config.riscv_baremetal_hardfloat
+
             if cls.is_baremetal() or cls.is_rtems():
                 # Both RTEMS and baremetal FreeRTOS are linked above 0x80000000
-                result.append("-mcmodel=medany")
+                result.append("-mcmodel=medium")
+
+            if config.riscv_cheri_gprel:
+                if xtarget.is_cheri_purecap():
+                    result.append("-cheri-cap-table-abi=gprel")
+
         elif xtarget.is_aarch64(include_purecap=True):
             fp_simd_option = AArch64FloatSimdOptions.SOFT if softfloat else config.aarch64_fp_and_simd_options
             march_suffix = fp_simd_option.clang_march_flag()

pycheribuild/projects/cross/compiler_rt.py

@@ -184,10 +184,14 @@ def install(self, **kwargs):
         if self.target_info.is_rtems():
             self.move_file(self.install_dir / "lib/rtems5" / libname, self.install_dir / "lib" / libname)
         elif self.target_info.is_baremetal():
-            self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / libname)
-            self.create_symlink(
-                self.install_dir / "lib" / libname, self.install_dir / "lib/libgcc.a", print_verbose_only=False
-            )
+            if self.config.riscv_cheri_gprel:
+                gprel_libname = "libclang_rt.builtins-" + self.triple_arch + "-gprel.a"
+                self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / gprel_libname)
+            else:
+                self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / libname)
+                self.create_symlink(
+                    self.install_dir / "lib" / libname, self.install_dir / "lib/libgcc.a", print_verbose_only=False
+                )
 
 
 class BuildUpstreamCompilerRtBuiltins(BuildCompilerRtBuiltins):