RISC-Style ALU on Tang Nano 9k FPGA

ALU in Verilog with 16 arithmetic, logic, and comparative operations. Equiped with self-checking testbench system.

Demos

4-Bit Demo with 7-Seg Display (code here)

ALU_4-Bit_Demo.mov

ALU Testbench Example Output

Waveform Generated

Features

• Scalable data width: (default 8-bit) for easy reuse and testing.
• Comprehensive Operation Set: Supports 16 operations like:
  
  • Arithmetic: ADD, SUB, MULTIPLY, DIVIDE
    
  • Bitwise Logic: AND, NAND, OR, NOR, XOR, XNOR
    
  • Comparison: EQUAL, GREATER_THAN, LESS_THAN
    
  • Barrel Shifting: ROTATE_LEFT, ROTATE_RIGHT
    
• Full Flag Generation: Correctly asserts Zero, Carry, Overflow, and Error flags based on operation results.
  
• Advanced Verification: Features a fully automated self-checking testbench with:
  • Custom bitmask-based error-tracking system for precise fault isolation.
  • Clear pass/fail report for reliability.
• FPGA Validated: Successfully synthesized and run on a Gowin Tang Nano 9K, with results displayed via a seven-segment display driver.

Operations Supported

Type	Operations
Arithmetic	ADD, SUB, MULT, DIVIDE
Logical	AND, OR, XOR, NAND, NOR, XNOR
Comparison	EQU, GREATER_THAN, LESS_THAN
Shift/Rotate	ROTATE_LEFT, ROTATE_RIGHT
Data Transfer	MFHI, MFLO

Tools

• HDL: Verilog
• FPGA: Gowin Tang Nano 9K (GW1NR-LV9)
• IDE: VSCode
• Extensions:
  
  • Verilog-HDL/SystemVerilog/Bluespec SystemVerilog by Masahiro Hiramori
    
  • WaveTrace by wavetrace
    
  • Lushay Code by Lushay Labs
    
• Simulation & Synthesis Tool: Icarus Verilog

Repository Structure

        /src        -> Verilog source files
        /tb         -> Testbench files
        /doc        -> Documentation, block diagrams
        /demo       -> Verilog source files synthesized on the FPGA

Roadmap

Phase 0: Validate Design Flow (Complete)

• FPGA Hardware Implementation (6-bit counter)

Phase 1: Core ALU (Complete)

• Arithmetic Operations (ADD, SUB with status flags)
• Bitwise Logic Unit (AND, OR, XOR, NAND, NOR, XNOR)
• Verification Suite (Self-checking testbench)
• FPGA Validation (6-bit counter hardware demo)

Phase 2: Enhanced Operations (Complete)

• Barrel Shifter (Logical & arithmetic shifts, rotates)
• Comparison Unit (EQU, GREATER_THAN, LESS_THAN)
• Multiplication & Division Unit (2x bit multiplication result)

Phase 3: System Integration (Complete)

• 8-bit Scalable Architecture (Parameterized design)
• Synthesize (Run full ALU on FPGA hardware)
• Seven-Segment Display Driver (Hex output for debugging)

Future Improvements:

• Control Unit Integration (Instruction decode & sequencing)

Useful Links

Verilog Cheat Sheet
Tang Nano 9k Information & Resources
Icarus Verilog
EDA Playground