Wishbone

Cores related to Wishbone:

• Wishbone Master Controller (master): Controls everything in a Wishbone based system. The master is designed to communicate with a host device using one of the 'host interface' cores. The master receives commands from the host interface and based on the specified command will initiate transactions on either the peripheral bus or the memory bus.
• Host Interface (host_interface): platform specific code used to interface with a custom hardware interface (such as a UART, High Speed FIFO or PCI Express) and translates those commands to the generic master.
• Interconnect (interconnect): Memory or Peripheral multiplexer between the master and peripheral or memory devices. This allows the one master with a single peripheral and memory bus to communicate with one or more devices.
• Arbiter (arbiter): Many to one connection. Used to allow multiple masters to control one device.
• Slave (slave): Wishbone based slaves. These cores contain both generic cores such as camera controllers or SPI hosts as well as the Wishbone slave cores that interface with the Wishbone bus. This Should be Decoupled!