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Wishbone Slaves
Dave edited this page Mar 11, 2016
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Slaves that are compatible with Wishbone bus.
- SDB: Self Defined Bus Core: This is essentially a ROM that is usually loaded with the Self Defined Bus created by Nysa scripts.
- BRAM: An inferred block RAM with a Wishbone Interface.
- DMA: Direct Memory Access with a Wishbone Interface.
- DMA Reader: Reads data from the DMA usually used to test out the DMA.
- DMA Writer: Writes data to the DMA usually used to test out the DMA.
- FPGA NES: FPGA Nintendo Entertainment System core.
- GPIO: Simple GPIOs with Wishbone Interface.
- HS Demo: Used to attach a simple block RAM to the DMA.
- I2C: I2C Master.
- I2S: Inter IC Sound core. This core only writes data out at 24bit stereo audio.
- I2S Reader: Inter IC Sound core. Work in progress!
- Logic Analyzer: Logic Analyzer. Work in progress!
- New Haven LCD: Streams video to a New Haven LCD Controller.
- SATA: Designed to interact with Nysa SATA.
- SD Host: Designed to interact with an SD Card or SDIO device.
- SDIO Device: SDIO Slave interface. This is used to test out the SDIO Host interface to be used on the Nyx board. Used to interface with Nysa SDIO Core.
- SDRAM: Core to interact with SDRAM chip.
- Sparkfun Camera: A core to read images from a parallel camera output for an old Sparkfun Camera.
- Seeed TFT: A core to interact with a Seeed studio Arduino LCD. Work in Progress!
- SPI: SPI Master Core.
- Stepper: A flexible stepper motor controller.
- Test DMA Mem: Another core used to test DMA core.
- UART: Universal Asynchronous Receive and Transmit.