Skip to content

Conversation

@bhusang
Copy link
Contributor

@bhusang bhusang commented Jun 10, 2024

No description provided.

@bhusang bhusang requested a review from callendorph June 10, 2024 21:55
@@ -0,0 +1,47 @@
#use-added-syntax(jitx)
defpackage jsl/examples/protocols/sata/SATA-main:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Package name is SATA instead of ARINC818

Comment on lines +62 to +67
public pcb-bundle ARINC818 (type:ARINC818Type) :
name = "ARINC818"
description = "ARINC 818 AVDB protocol"
switch(type) :
TX : make-port(`TX, diff-pair)
RX : make-port(`RX, diff-pair)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

For other unidirectional standards like DisplayPort, we don't differentiate between transmit and receive.

It feels like this attempting to implement a Cardinality style implementation. Ie - this is a output, this is an input, kind of thing.

Side note - is the ARINC818 really just a diff-pair ? Do we have a copy of the spec ?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The standard is just a uni-directional diff-pair modeled on FiberChannel but the physical layer implementation is pretty well unspecified. I was trying to force an ordering by the type of bundle (TX -> RX) only.

@param p-tx The TX pin
@param p-rx The RX pin
<DOC>
public defn check-correct-pins (p-tx:JITXObject p-rx:JITXObject):
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

We have a check-single-pin already:

public defn check-single-pin (p-set:JITXObject ...):

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yep, tried to use that first. But the error message would not make sense in the context that you did not connect the TX to RX but instead connected RX to TX. The reason to make this directional is that some implementations are optical and in that case, you need some more directionality?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants