Complete Tile IR 13.4 raw APIs, target gates, and unsafe PDL

[elibol]

Executive summary

Add the approved raw Tile IR 13.4 surface and previously missing 13.3
controls. JIT compilation checks both the selected assembler's bytecode
version and the actual device architecture, including configuration-specific
restrictions, before calling tileiras. Bytecode selection follows the
selected executable (including CUTILE_TILEIRAS_PATH), not build-time headers.
CUDA 13.2/13.3 keep their wire layouts and reject newer nondefault options.

PDL is an unsafe, disabled-by-default per-launch opt-in on the existing
builder. The consumer opts in and token-orders dependent accesses after
gdc_wait_tko. Driver lookup is runtime-only; an unavailable extended launch
entry point returns unsupported rather than silently dropping the request.

API surface changes

• Raw core ops: insert, fpowi, fpowf (pow remains), GDC launch/wait tokens,
  memory_fence_alias_tko, and local/global alloca.
• f8e5m3fnu; NearestIntToZero/NearestAway rounding markers; explicit
  saturating ftoi, pointer classification, fast-accumulation MMA and
  exp/tanh rounding controls.
• Arbitrary-rank raw view load/store/reduction with explicit tokens,
  ordering/scope, hints and inbounds promises; complete padding choices.
• Full-width/general-rank raw assumption predicates; module producer
  metadata and constant/private Global annotations.
• Kernel returns inside loop/while on 13.4. Returns beneath for and nested
  helper returns remain restricted, without changing helper-return semantics.
• Unsafe programmatic_dependent_launch on generated builders and
  AsyncKernelLaunch; cuda_core::api::launch_kernel_pdl.
• BytecodeVersion::V13_4, pointer-attribute/type/opcode additions, target
  capability validation, and compile-only bytecode_version selection.
• Existing function signatures and default launch serialization are unchanged.

FP4 is supported on SM120/121. The new f8E5M3FNU scaled-MMA configuration
requires SM107 specifically; it is not a numeric “SM100 only” restriction
on all FP4 operations.

Validation

• CPU and GPU runner scripts with CUDA 13.3 and the selected CUDA 13.4
  assembler; serial execution for process-global cache/timing-sensitive tests.
• cutile-ir all-version roundtrips, exact wire-layout tests and differential
  checks against an external cuTile Python encoder checkout (not vendored).
• Exact spanned refusal tests: insert_refuses_13_3_before_tileiras_with_source_span
  and scale_format_refuses_sm_120_even_with_13_4. Positive SM107 compile-only
  coverage and an execution test gated on that hardware.
• GPU execution on RTX 5090: PDL producer/consumer, new arithmetic/rounding,
  insert, fast accumulation, allocation, globals, classified pointers,
  gather/scatter, strided reduction and conditional kernel return.
• CUDA 13.0 shared-host-crate build, formatting and nightly workspace clippy.
• Unsafe-contract review covers token causality, allocation lifetime,
  raw-view aliasing/bounds, launch ABI, runtime lookup and inline return scope.

No SM107 hardware was available for execution. CI retains the 13.3 build and
13.0 host floor; the added 13.4 lane activates when CUDA_13_4_IMAGE is set.

Pinned refusal messages

insert_refuses_13_3_before_tileiras_with_source_span:

cuda_tile.insert requires Tile IR 13.4 or newer; selected Tile IR 13.3, target sm_120

scale_format_refuses_sm_120_even_with_13_4:

cuda_tile.mmaf_scaled with f8E5M3FNU scales requires sm_107; selected Tile IR 13.4, target sm_120

Both tests also assert the original Rust source location.