Added support for board nucleo u545re q

Cargo.lock

@@ -926,6 +926,7 @@ dependencies = [
  "ecdsa-sw",
  "kernel",
  "nrf52840",
+ "nrf52840dk-test-base",
  "nrf52_components",
  "segger",
  "tock-tbf",
@@ -943,6 +944,7 @@ dependencies = [
  "cortexm4",
  "kernel",
  "nrf52840",
+ "nrf52840dk-test-base",
  "nrf52_components",
  "segger",
  "tock_build_scripts",
@@ -959,11 +961,27 @@ dependencies = [
  "cortexm4",
  "kernel",
  "nrf52840",
+ "nrf52840dk-test-base",
  "nrf52_components",
  "segger",
  "tock_build_scripts",
 ]
 
+[[package]]
+name = "nrf52840dk-test-base"
+version = "0.2.3-dev"
+dependencies = [
+ "capsules-core",
+ "capsules-extra",
+ "capsules-system",
+ "components",
+ "cortexm4",
+ "kernel",
+ "nrf52840",
+ "nrf52_components",
+ "segger",
+]
+
 [[package]]
 name = "nrf52840dk-test-dynamic-app-load"
 version = "0.2.3-dev"
@@ -991,6 +1009,7 @@ dependencies = [
  "cortexm4",
  "kernel",
  "nrf52840",
+ "nrf52840dk-test-base",
  "nrf52_components",
  "segger",
  "tock_build_scripts",
@@ -1093,6 +1112,20 @@ dependencies = [
  "tock_build_scripts",
 ]
 
+[[package]]
+name = "nucleo_u545re_q"
+version = "0.2.3-dev"
+dependencies = [
+ "capsules-core",
+ "capsules-extra",
+ "capsules-system",
+ "components",
+ "cortexm33",
+ "kernel",
+ "stm32u545",
+ "tock_build_scripts",
+]
+
 [[package]]
 name = "opaque-debug"
 version = "0.3.1"
@@ -1582,6 +1615,23 @@ dependencies = [
  "kernel",
 ]
 
+[[package]]
+name = "stm32u545"
+version = "0.2.3-dev"
+dependencies = [
+ "cortexm33",
+ "kernel",
+ "stm32u5xx",
+]
+
+[[package]]
+name = "stm32u5xx"
+version = "0.2.3-dev"
+dependencies = [
+ "cortexm33",
+ "kernel",
+]
+
 [[package]]
 name = "stm32wle5jc"
 version = "0.2.3-dev"

Cargo.toml

@@ -40,6 +40,7 @@ members = [
     "boards/sma_q3",
     "boards/nucleo_f429zi",
     "boards/nucleo_f446re",
+    "boards/nucleo_u545re_q",
     "boards/particle_boron",
     "boards/pico_explorer_base",
     "boards/raspberry_pi_pico",
@@ -61,6 +62,7 @@ members = [
     "boards/configurations/nrf52840dk/nrf52840dk-test-appid-ecdsap256",
     "boards/configurations/nrf52840dk/nrf52840dk-test-appid-sha256",
     "boards/configurations/nrf52840dk/nrf52840dk-test-appid-tbf",
+    "boards/configurations/nrf52840dk/nrf52840dk-test-base",
     "boards/configurations/nrf52840dk/nrf52840dk-test-invs",
     "boards/configurations/nrf52840dk/nrf52840dk-test-kernel",
     "boards/configurations/nrf52840dk/nrf52840dk-test-dynamic-app-load",
@@ -109,6 +111,8 @@ members = [
     "chips/stm32f429zi",
     "chips/stm32f446re",
     "chips/stm32f412g",
+    "chips/stm32u545",
+    "chips/stm32u5xx",
     "chips/stm32f4xx",
     "chips/veer_el2",
     "chips/stm32wle5xx",

arch/cortex-m33/src/lib.rs

@@ -25,6 +25,7 @@ pub mod mpu {
     }
 }
 
+pub use cortexm::dma_fence;
 pub use cortexm::initialize_ram_jump_to_main;
 pub use cortexm::interrupt_mask;
 pub use cortexm::nvic;

arch/riscv/src/csr/mod.rs

@@ -5,18 +5,21 @@
 //! Tock Register interface for using CSR registers.
 
 use riscv_csr::csr::{
-    ReadWriteRiscvCsr, MCAUSE, MCYCLE, MCYCLEH, MEPC, MIE, MINSTRET, MINSTRETH, MIP, MSCRATCH,
-    MSECCFG, MSECCFGH, MSTATUS, MTVAL, MTVEC, PMPADDR0, PMPADDR1, PMPADDR10, PMPADDR11, PMPADDR12,
-    PMPADDR13, PMPADDR14, PMPADDR15, PMPADDR16, PMPADDR17, PMPADDR18, PMPADDR19, PMPADDR2,
-    PMPADDR20, PMPADDR21, PMPADDR22, PMPADDR23, PMPADDR24, PMPADDR25, PMPADDR26, PMPADDR27,
-    PMPADDR28, PMPADDR29, PMPADDR3, PMPADDR30, PMPADDR31, PMPADDR32, PMPADDR33, PMPADDR34,
-    PMPADDR35, PMPADDR36, PMPADDR37, PMPADDR38, PMPADDR39, PMPADDR4, PMPADDR40, PMPADDR41,
-    PMPADDR42, PMPADDR43, PMPADDR44, PMPADDR45, PMPADDR46, PMPADDR47, PMPADDR48, PMPADDR49,
-    PMPADDR5, PMPADDR50, PMPADDR51, PMPADDR52, PMPADDR53, PMPADDR54, PMPADDR55, PMPADDR56,
-    PMPADDR57, PMPADDR58, PMPADDR59, PMPADDR6, PMPADDR60, PMPADDR61, PMPADDR62, PMPADDR63,
-    PMPADDR7, PMPADDR8, PMPADDR9, PMPCFG0, PMPCFG1, PMPCFG10, PMPCFG11, PMPCFG12, PMPCFG13,
-    PMPCFG14, PMPCFG15, PMPCFG2, PMPCFG3, PMPCFG4, PMPCFG5, PMPCFG6, PMPCFG7, PMPCFG8, PMPCFG9,
-    STVEC, UTVEC,
+    ReadWriteRiscvCsr, MCAUSE, MCYCLE, MEPC, MIE, MINSTRET, MIP, MSCRATCH, MSECCFG, MSTATUS, MTVAL,
+    MTVEC, PMPADDR0, PMPADDR1, PMPADDR10, PMPADDR11, PMPADDR12, PMPADDR13, PMPADDR14, PMPADDR15,
+    PMPADDR16, PMPADDR17, PMPADDR18, PMPADDR19, PMPADDR2, PMPADDR20, PMPADDR21, PMPADDR22,
+    PMPADDR23, PMPADDR24, PMPADDR25, PMPADDR26, PMPADDR27, PMPADDR28, PMPADDR29, PMPADDR3,
+    PMPADDR30, PMPADDR31, PMPADDR32, PMPADDR33, PMPADDR34, PMPADDR35, PMPADDR36, PMPADDR37,
+    PMPADDR38, PMPADDR39, PMPADDR4, PMPADDR40, PMPADDR41, PMPADDR42, PMPADDR43, PMPADDR44,
+    PMPADDR45, PMPADDR46, PMPADDR47, PMPADDR48, PMPADDR49, PMPADDR5, PMPADDR50, PMPADDR51,
+    PMPADDR52, PMPADDR53, PMPADDR54, PMPADDR55, PMPADDR56, PMPADDR57, PMPADDR58, PMPADDR59,
+    PMPADDR6, PMPADDR60, PMPADDR61, PMPADDR62, PMPADDR63, PMPADDR7, PMPADDR8, PMPADDR9, PMPCFG0,
+    PMPCFG10, PMPCFG12, PMPCFG14, PMPCFG2, PMPCFG4, PMPCFG6, PMPCFG8, STVEC, UTVEC,
+};
+#[cfg(not(target_arch = "riscv64"))]
+use riscv_csr::csr::{
+    MCYCLEH, MINSTRETH, MSECCFGH, PMPCFG1, PMPCFG11, PMPCFG13, PMPCFG15, PMPCFG3, PMPCFG5, PMPCFG7,
+    PMPCFG9,
 };
 use tock_registers::fields::FieldValue;
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
@@ -51,7 +54,10 @@ pub struct CSR {
     pub mcycleh: ReadWriteRiscvCsr<usize, mcycle::mcycleh::Register, MCYCLEH>,
     pub mcycle: ReadWriteRiscvCsr<usize, mcycle::mcycle::Register, MCYCLE>,
 
-    #[cfg(not(target_arch = "riscv64"))]
+    // `pmpcfg0` exists on both RV32 and RV64. On RV64 each `pmpcfgN` is XLEN-wide
+    // and holds 8 entries, so only the even-indexed registers (pmpcfg0, 2, 4, …,
+    // 14) are valid; the odd-indexed ones below are RV32-only. `pmpcfg0` is the
+    // first of those even-indexed registers and must always be present.
     pub pmpcfg0: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG0>,
     #[cfg(not(target_arch = "riscv64"))]
     pub pmpcfg1: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG1>,
@@ -313,7 +319,9 @@ impl CSR {
     // reads the cycle counter
     #[cfg(target_arch = "riscv64")]
     pub fn read_cycle_counter(&self) -> u64 {
-        CSR.mcycle.read(mcycle::mcycle::mcycle)
+        // On RV64 `mcycle` is a single 64-bit CSR; `read` returns `usize`, which
+        // is `u64` here but still needs an explicit cast to the return type.
+        CSR.mcycle.read(mcycle::mcycle::mcycle) as u64
     }
 
     pub fn pmpconfig_get(&self, index: usize) -> usize {