Added support for board nucleo u545re q by FarhadGUL06 · Pull Request #12 · OxidosAutomotive/tock

FarhadGUL06 · 2026-04-06T20:23:24Z

Pull Request Overview

This pull request adds support for the Nucleo-U545RE-Q board (STM32U545) to Tock OS. It introduces a new stm32u5xx chip crate designed for the ultra-low-power STM32U5 series, with a specific focus on Secure Mode operation and TrustZone compatibility.

Features implemented:

New Chip Crate (stm32u5xx): implementation of core peripherals (RCC, GPIO, EXTI, TIM, USART).
Async USART with DMA: Serial driver using GPDMA engine for background transmission (TX) and IRQs for reliable, low-latency reception (RX) via a 32-byte circular FIFO.
GPIO & EXTI: Fully asynchronous interrupt handling for board buttons and LED.
Alarm HIL: Implemented TIM2 as the timekeeper for both kernel and apps.
Multi-Process Support: Configured for up to 4 simultaneous userspace applications with 64KB+ of sandbox RAM. (Note: Currently tested with 1 app; further multi-app verification is pending tockloader integration).

Testing Strategy

This pull request was tested on a physical Nucleo-U545RE-Q hardware target.

Deployment: Deployment was performed using probe-rs.
Functionality:
-- Verified kernel boot and console output at 115200 baud via USART1.
-- Verified that the User Button (PC13) triggers asynchronous interrupts to toggle the User LED (PA5).
-- Verified userspace delay_ms functionality using the TIM2-backed Alarm HIL.
-- Validated the GPDMA1 configuration (Request ID 25) for stable background printing.

TODO or Help Wanted

This pull request still needs:

Tockloader Support: Investigating why the OpenOCD stm32u5x target configuration fails to identify the board automatically in WSL environments.
Multi-App Validation: Once tockloader is functional, perform stress tests with multiple concurrent processes to verify the 64KB sandbox allocation.
Extended Peripheral Support: Add more peripherals.

Documentation Updated

No updates required (Follows existing Tock architectural patterns).

Formatting

Ran make prepush.
Ran cargo fmt.

AI Use

The PR description details my use of AI in the production of the code in this PR. This port was developed with the assistance of an AI engineering agent (Gemini CLI). All generated code, register offsets, and memory maps were manually verified against the STM32U545 Reference Manual and validated on live hardware.

Copilot

Pull request overview

This PR adds initial support for the ST Nucleo-U545RE-Q board by introducing new STM32U5 chip support crates (stm32u5xx + stm32u545) and wiring up a board target (nucleo_u545re_q) to boot Tock, provide console I/O over USART1, basic GPIO/EXTI for button/LED, and a TIM2-backed Alarm.

Changes:

Added new stm32u5xx chip crate implementing RCC, GPIO/EXTI, TIM2 alarm, USART1, and GPDMA-based TX plumbing.
Added stm32u545 chip wrapper crate and a new nucleo_u545re_q board target (linker layout, kernel main, flashing helpers).
Registered new workspace members and updated board listings.

Reviewed changes

Copilot reviewed 21 out of 24 changed files in this pull request and generated 12 comments.

Show a summary per file

File	Description
chips/stm32u5xx/src/usart.rs	New USART implementation with DMA TX and IRQ-driven RX FIFO.
chips/stm32u5xx/src/tim.rs	New TIM2-based `Time`/`Alarm` implementation.
chips/stm32u5xx/src/rcc.rs	Minimal RCC clock-enable helpers for STM32U5 peripherals.
chips/stm32u5xx/src/lib.rs	New STM32U5 crate root (vectors + init + peripheral bundle).
chips/stm32u5xx/src/gpio.rs	New GPIO pin/port implementation with EXTI integration.
chips/stm32u5xx/src/exti.rs	New EXTI implementation with line routing/masking and client dispatch.
chips/stm32u5xx/src/dma.rs	New GPDMA register mapping and USART1 TX/RX setup routines.
chips/stm32u5xx/src/chip.rs	New chip-level interrupt dispatch and `Chip` trait implementation.
chips/stm32u5xx/Cargo.toml	Declares the new `stm32u5xx` crate and dependencies.
chips/stm32u545/src/lib.rs	New STM32U545 wrapper crate re-exporting `stm32u5xx`.
chips/stm32u545/Cargo.toml	Declares the new `stm32u545` crate and dependency on `stm32u5xx`.
chips/stm32f4xx/src/gpio.rs	Minor formatting-only change in existing STM32F4 GPIO enum.
Cargo.toml	Adds new board and chip crates to the workspace members list.
Cargo.lock	Adds lock entries for the new board/chip crates.
boards/README.md	Registers the new Nucleo-U545RE-Q (skeleton) board in the boards list.
boards/nucleo_u545re_q/src/main.rs	New board main: sets up peripherals, capsules, NVIC routing, and process loading.
boards/nucleo_u545re_q/src/io.rs	Board debug/panic writer using a polled USART1 write loop.
boards/nucleo_u545re_q/Makefile	Adds probe-rs and J-Link flashing/build helpers (kernel + merged app).
boards/nucleo_u545re_q/layout.ld	Board linker layout including appmem symbols and stack override.
boards/nucleo_u545re_q/flash.jlink	J-Link script for loading the merged binary at the secure flash alias.
boards/nucleo_u545re_q/chip_layout.ld	Defines secure-alias memory map for kernel/apps/ram regions.
boards/nucleo_u545re_q/Cargo.toml	Declares the new board crate and capsule/component dependencies.
boards/nucleo_u545re_q/.cargo/config.toml	Sets the build target and includes shared Tock cargo flags.

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Copilot · 2026-04-06T20:28:10Z

+    fn handle_deferred_call(&self) {
+        // 1. Transmit Completion (DMA)
+        if let Some(buf) = self.tx_buffer.take() {
+            let len = self.tx_len.get();
+            self.tx_client.map(move |client| {
+                client.transmitted_buffer(buf, len, Ok(()));
+            });
+        }
+
+        // 2. Receive Completion (FIFO)
+        self.try_receive_from_fifo();
+    }


handle_deferred_call() unconditionally takes tx_buffer and signals transmitted_buffer(). Because the deferred call is also scheduled from the RX IRQ path, an RX interrupt can cause an in-progress DMA TX to be reported as complete early and return the buffer while DMA is still reading it (potential memory corruption). Track TX completion separately (e.g., a tx_done flag set only in the DMA TX ISR) and only return the TX buffer when the DMA completion interrupt has occurred.

Copilot · 2026-04-06T20:28:10Z

+        while regs.isr.is_set(ISR::RXNE) {
+            let byte = regs.rdr.get() as u8;
+            let mut f = self.fifo.get();
+            let w = self.fifo_write.get();
+            f[w % 32] = byte;
+            self.fifo.set(f);
+            self.fifo_write.set(w + 1);
+            data_received = true;
+        }
+


The RX FIFO bookkeeping has no overflow handling: fifo_write increments without bound and bytes are always written to f[w % 32], overwriting unread data when more than 32 bytes arrive before the reader drains the FIFO. Consider implementing a true ring buffer with a bounded count (or dropping/flagging overflow) so data loss is deterministic and detectable.

Suggested change

while regs.isr.is_set(ISR::RXNE) {

let byte = regs.rdr.get() as u8;

let mut f = self.fifo.get();

let w = self.fifo_write.get();

f[w % 32] = byte;

self.fifo.set(f);

self.fifo_write.set(w + 1);

data_received = true;

}

let mut f = self.fifo.get();

let mut r = self.fifo_read.get();

let mut w = self.fifo_write.get();

// Keep the counters bounded while preserving the number of unread bytes.

while r >= f.len() && w >= f.len() {

r -= f.len();

w -= f.len();

}

self.fifo_read.set(r);

while regs.isr.is_set(ISR::RXNE) {

let byte = regs.rdr.get() as u8;

if (w - r) < f.len() {

f[w % f.len()] = byte;

w += 1;

data_received = true;

} else {

// FIFO full: drop the new byte rather than overwrite unread data.

}

}

self.fifo.set(f);

self.fifo_write.set(w);

Please verify this.

I changed to dma rx

Copilot · 2026-04-06T20:28:11Z

+                dma.clear_interrupt(self.dma_channel_tx.get());
+            });
+            self.registers.cr3.modify(CR3::DMAT::CLEAR);
+            self.deferred_call.set();


handle_dma_interrupt(false) is a no-op. Since the chip interrupt table enables a DMA RX IRQ and routes it here, this can leave the DMA RX interrupt pending and retriggering continuously. Either clear the RX channel interrupt flags in the !is_tx branch (and/or disable the RX IRQ if unused).

Suggested change

self.deferred_call.set();

self.deferred_call.set();

} else {

self.dma.map(|dma| {

dma.clear_interrupt(self.dma_channel_rx.get());

});

Copilot · 2026-04-06T20:28:12Z

+        // Clear pending flags for this line
+        self.registers.rpr1.set(1 << line);
+        self.registers.fpr1.set(1 << line);
+
+        // Notify the client directly
+        if line < 16 {
+            self.clients[line].map(|client| {
+                client.fired();
+            });
+        }


handle_interrupt() writes 1 << line to clear pending bits before validating line < 16. If this is ever called with an out-of-range value, the shift can panic in debug builds or behave unexpectedly. Perform the bounds check before any shifts/writes.

Suggested change

// Clear pending flags for this line

self.registers.rpr1.set(1 << line);

self.registers.fpr1.set(1 << line);

// Notify the client directly

if line < 16 {

self.clients[line].map(|client| {

client.fired();

});

}

if line >= 16 {

return;

}

// Clear pending flags for this line

self.registers.rpr1.set(1 << line);

self.registers.fpr1.set(1 << line);

// Notify the client directly

self.clients[line].map(|client| {

client.fired();

});

Agree to this. if you want to avoid an if, define an enum that does not exceed the possible values.

Changed to pub fn handle_interrupt(&self, line: LineId) and added let line_num = line as usize;. This way, we are sure that line_num < 16.

Copilot · 2026-04-06T20:28:12Z

+    client: OptionalCell<&'a dyn time::AlarmClient>,
+}
+
+impl<'a> Tim2<'a> {
+    pub const fn new(base: StaticRef<TimRegisters>) -> Tim2<'a> {
+        Tim2 {
+            registers: base,
+            client: OptionalCell::empty(),
+        }
+    }
+
+    pub fn enable_clock(&self) {
+        // Secure Alias for RCC_APB1ENR1
+        let rcc_apb1enr1 = 0x46020C9C as *mut u32;
+        unsafe {
+            core::ptr::write_volatile(rcc_apb1enr1, core::ptr::read_volatile(rcc_apb1enr1) | 1);
+        }


enable_clock() directly reads/writes a hard-coded RCC register address via raw pointers. This duplicates rcc::Rcc::enable_tim2() and makes the clocking path harder to audit/maintain. Prefer using the existing RCC abstraction (or pass an Rcc reference into the timer) instead of embedding literal addresses here.

Suggested change

client: OptionalCell<&'a dyn time::AlarmClient>,

}

impl<'a> Tim2<'a> {

pub const fn new(base: StaticRef<TimRegisters>) -> Tim2<'a> {

Tim2 {

registers: base,

client: OptionalCell::empty(),

}

}

pub fn enable_clock(&self) {

// Secure Alias for RCC_APB1ENR1

let rcc_apb1enr1 = 0x46020C9C as *mut u32;

unsafe {

core::ptr::write_volatile(rcc_apb1enr1, core::ptr::read_volatile(rcc_apb1enr1) | 1);

}

enable_clock: fn(),

client: OptionalCell<&'a dyn time::AlarmClient>,

}

impl<'a> Tim2<'a> {

pub const fn new(base: StaticRef<TimRegisters>, enable_clock: fn()) -> Tim2<'a> {

Tim2 {

registers: base,

enable_clock,

client: OptionalCell::empty(),

}

}

pub fn enable_clock(&self) {

(self.enable_clock)();

Agree with this.

Added enable_clock to pub struct Tim2<'a>

Copilot · 2026-04-06T20:28:13Z

+impl<'a> uart::Configure for Usart<'a> {
+    fn configure(&self, _params: uart::Parameters) -> Result<(), kernel::ErrorCode> {
+        let regs = &*self.registers;
+        regs.cr1.modify(CR1::UE::CLEAR);
+        regs.presc.set(0);
+        regs.brr.set(35);
+        regs.icr.set(0x3F);
+        // Hybrid: RXNEIE is ENABLED for typing interrupts
+        regs.cr1
+            .write(CR1::TE::SET + CR1::RE::SET + CR1::UE::SET + CR1::RXNEIE::SET);
+        Ok(())


configure() ignores the supplied uart::Parameters (baud rate, stop bits, parity, width, etc.) and instead hardcodes presc=0 and brr=35. This makes the UART configuration API misleading and will break any caller expecting non-115200 settings (or different clocking). Use params to compute BRR/prescaler and configure CR2 STOP/parity/word length as appropriate, or return NOSUPPORT/INVAL for unsupported modes.

alexandruradovici · 2026-04-07T10:15:18Z

+
+impl IoWrite for Writer {
+    fn write(&mut self, buf: &[u8]) -> usize {
+        // Literal Secure Alias for USART1


Is there any reason why we do not use the UART implementation from the chip crate? We cannot assume that the UART has already been configured before a panic.

I centralized the UART base address as a constant in the chip crate and implemented a synchronous transmit_byte method to ensure panic reporting even when the DMA is unavailable.

alexandruradovici · 2026-04-07T10:15:42Z

+            stm32u545::tim::Tim2<'static>,
+        >,
+    >,
+    ipc: kernel::ipc::IPC<4>,


Do not implement IPC, it is not working and the kernel receives a None IPC.

I removed ipc

alexandruradovici · 2026-04-08T10:07:12Z

+    let exti = static_init!(
+        stm32u545::exti::Exti<'static>,
+        stm32u545::exti::Exti::new(StaticRef::new(
+            0x56022000 as *const stm32u545::exti::ExtiRegisters
+        ))
+    );
+
+    let dma1 = static_init!(
+        stm32u545::dma::Dma,
+        stm32u545::dma::Dma::new(StaticRef::new(
+            0x50020000 as *const stm32u545::dma::DmaRegisters
+        ))
+    );
+
+    let usart1 = static_init!(
+        stm32u545::usart::Usart<'static>,
+        stm32u545::usart::Usart::new(StaticRef::new(
+            0x50013800 as *const stm32u545::usart::UsartRegisters
+        ))
+    );


I would create init functions for these inside the chip crate.

Created init function for each of those in their file

alexandruradovici · 2026-04-08T10:11:05Z

+    let button_pins = static_init!(
+        [(
+            &'static kernel::hil::gpio::InterruptValueWrapper<'static, stm32u545::gpio::Pin>,
+            kernel::hil::gpio::ActivationMode,
+            kernel::hil::gpio::FloatingState
+        ); 1],
+        [(
+            button_pin,
+            kernel::hil::gpio::ActivationMode::ActiveHigh,
+            kernel::hil::gpio::FloatingState::PullDown
+        )]
+    );


Please use the button_component_helper! helper macro similar to https://github.com/tock/tock/blob/b45c546122a747f7a7575179473cbb7c7fc048a0/boards/microbit_v2/src/main.rs#L329-L346.

Changed to use button_component_helper!

alexandruradovici · 2026-04-16T14:29:41Z

+// IRQ Numbers
+const EXTI13_IRQ: u32 = 24;
+const GPDMA1_CH0_IRQ: u32 = 29;
+const GPDMA1_CH1_IRQ: u32 = 30;
+const TIM2_IRQ: u32 = 45;
+const USART1_IRQ: u32 = 61;


I suggest putting these in a separate file that only lists the interrupts.

alexandruradovici · 2026-04-16T14:32:33Z

+            regs.icr.set(0x0F);
+        }
+
+        // 2. Receive Logic: Drain the Hardware FIFO.


Suggested change

// 2. Receive Logic: Drain the Hardware FIFO.

// Receive Logic: Drain the Hardware FIFO.

What the 2. required?

alexandruradovici · 2026-04-16T14:34:28Z

+        // 2. Receive Logic: Drain the Hardware FIFO.
+        // Used a 'while' loop here to ensure that every byte currently
+        // waiting in the hardware Receive Data Register (RDR) is moved into
+        // the software FIFO. In high-speed scenarios, multiple bytes may


What do we need the software FIFO? Can't we use the received buffer?

The reason I implemented a software FIFO was related to the up and down arrows. If I don't use it, I can't get the arrows to work. I was only able to get them to work by using a software FIFO. The arrows are sequences of 3 characters

alexandruradovici · 2026-04-16T14:36:25Z

+///
+/// This ensures that long-running application callbacks are executed in
+/// the kernel's main loop context rather than within the high-priority
+/// hardware interrupt handler. This prevents the console from blocking


Tock uses only bottom halves interrupt handling, everything is a deferred call.

I used deffered + software fifo to get arrow up and down to work. I switched to dma even for rx and it seems to work fine

alexandruradovici · 2026-04-16T14:39:11Z

+        while regs.isr.is_set(ISR::RXNE) {
+            let byte = regs.rdr.get() as u8;
+            let mut f = self.fifo.get();
+            let w = self.fifo_write.get();
+            f[w % 32] = byte;
+            self.fifo.set(f);
+            self.fifo_write.set(w + 1);
+            data_received = true;
+        }
+


Please verify this.

alexandruradovici · 2026-04-18T11:37:27Z

+        base: StaticRef<GpioRegisters>,
+        pin: usize,
+        exti: &'a Exti<'a>,
+        port_id: GpioPortNumber,


I suggest using the port

Suggested change

port_id: GpioPortNumber,

port: Port,

alexandruradovici · 2026-04-18T11:38:33Z

+
+//! Named constants for NVIC ids shared across the stm32u5xx family of chips
+
+#![allow(non_upper_case_globals)]


Suggested change

#![allow(non_upper_case_globals)]

alexandruradovici · 2026-04-18T11:40:42Z

+            return Err((kernel::ErrorCode::BUSY, tx_buffer));
+        }
+
+        if self.dma.is_none() {


Please use let else to avoid aouble checking (here and when using map.

alexandruradovici · 2026-04-18T11:41:07Z

+            return Err((kernel::ErrorCode::BUSY, rx_buffer));
+        }
+
+        if self.dma.is_none() {


Please use let else.

alexandruradovici · 2026-04-21T09:21:27Z

+/* 
+ * Define the application memory symbols so the Tock kernel
+ * knows where to look for processes at boot.
+ */
+_sappmem = ORIGIN(prog);
+_eappmem = ORIGIN(prog) + LENGTH(prog);
+
+/* 
+ * Override _estack after including the generic layout.
+ */
+_estack = ORIGIN(ram) + LENGTH(ram);


I don't see this for other boards, do we need it?

Other boards (like nucleo_f429zi) include this in main.rs as extern "C". I moved it from layout.ld to main.rs

alexandruradovici · 2026-04-21T09:23:57Z

+            exti,
+            dma1,
+            gpio_a: gpio::Port::new(
+                StaticRef::new(0x52020000 as *const gpio::GpioRegisters),


Please define the StaticRef sa a constant named PORT_A_ADDRESS or similar.

alexandruradovici · 2026-04-21T09:25:08Z

+        usart1: &'a usart::Usart<'a>,
+    ) -> Self {
+        Self {
+            rcc: rcc::Rcc::new(StaticRef::new(0x46020C00 as *const rcc::RccRegisters)),


Suggested change

rcc: rcc::Rcc::new(StaticRef::new(0x46020C00 as *const rcc::RccRegisters)),

rcc: rcc::Rcc::new(RCC_BASE),

alexandruradovici · 2026-04-21T09:27:40Z

+                );
+            });
+        }
+        Ok(())


Suggested change

Ok(())

This allows a ring buffer to be safely created with a `ring` of uninitialized memory.

Fix in process standard and in debug writer component.

extract rather than copy?

FarhadGUL06 requested review from alexandruradovici and Copilot April 6, 2026 20:23

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FarhadGUL06 force-pushed the board_nucleo_u545re_q branch from 34b8590 to 07eb27c Compare April 27, 2026 13:31

github-actions Bot added HIL kernel nrf sam4l WG-OpenTitan WG-Network WG-Crypto labels Apr 27, 2026

FarhadGUL06 force-pushed the board_nucleo_u545re_q branch from 3042c2c to f64e7b7 Compare May 10, 2026 09:56

github-actions Bot removed nrf sam4l WG-OpenTitan labels May 10, 2026

bradjc added 4 commits May 12, 2026 10:57

kernel: ring buffer: use MaybeUninit<T>

467f48f

This allows a ring buffer to be safely created with a `ring` of uninitialized memory.

update to MaybeUninit RingBuffer

6c98946

Fix in process standard and in debug writer component.

kernel: ring buffer: require T be Copy

609cf0d

kernel: ring buffer: use assume_init (no _read)

330a191

extract rather than copy?

FarhadGUL06 added 18 commits June 18, 2026 11:07

gpio: Changed to use tock-registers

c7dbe13

rcc: Changed to use tock-registers

29d2318

tim: Changed to use tock-registers

ab081fa

usart: Changed to use tock-registers

2061ea5

usart: modified one line to use tock-register

3dddadc

dma: added more tock-registers

8f3b691

cargo: removed enum_primitive

2a19122

Combined Stm32u5xxPeripherals and Stm32u5xxDefaultPeripherals

3e7d4bc

chips: added init function

d1578c2

io: changed to PanicWriter

abca0cf

usart: added dmaslice

5cf7367

Removed Writer and usart conf

ae819ef

dma: Removed match_channel function

386cee4

exti: added if check for line_num

2a22f81

usart: changed ok and busy on abort

b78da11

usart: changed to use deferred call

002ff7c

dma: added comment for channelid

2ea89e6

chips: stm32u5xx: Implement required Chip::init()

42328cd

FarhadGUL06 force-pushed the board_nucleo_u545re_q branch from d41d50e to 42328cd Compare June 18, 2026 08:14

github-actions Bot added HIL component nrf sam4l WG-OpenTitan risc-v and removed WG-Crypto labels Jun 18, 2026

FarhadGUL06 added 3 commits June 18, 2026 17:50

lib: removed init

9958f01

main.rs: added init call

770d7e5

Makefile: Changed from openocd to probe-rs for better stability

a31a6fa

alexandruradovici merged commit 44310bd into master Jul 21, 2026
19 checks passed

-            self.deferred_call.set();
+            self.deferred_call.set();
+        } else {
+            self.dma.map(|dma| {
+                dma.clear_interrupt(self.dma_channel_rx.get());
+            });

	// 2. Receive Logic: Drain the Hardware FIFO.
	// Receive Logic: Drain the Hardware FIFO.


		//! Named constants for NVIC ids shared across the stm32u5xx family of chips

		#![allow(non_upper_case_globals)]

	rcc: rcc::Rcc::new(StaticRef::new(0x46020C00 as *const rcc::RccRegisters)),
	rcc: rcc::Rcc::new(RCC_BASE),

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FarhadGUL06 commented Apr 6, 2026 •

edited

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