Funny Monkey Coding (FMC) Time

CMakeLists.txt

@@ -44,7 +44,8 @@ target_sources(${PROJECT_NAME} PRIVATE
         src/core/dev/RTCTimer.cpp
         src/core/dev/storage/M24C32.cpp
         src/core/dev/Thermistor.cpp
-        src/core/utils/log.cpp)
+        src/core/utils/log.cpp
+        src/core/io/FMC.cpp)
 
 get_directory_property(COMPDEFS COMPILE_DEFINITIONS)
 if(COMPDEFS MATCHES "(.*)STM32F3xx(.*)")
@@ -76,7 +77,9 @@ elseif(COMPDEFS MATCHES "(.*)STM32F4xx(.*)")
     src/core/io/platform/f4xx/SPIf4xx.cpp
     src/core/dev/platform/f4xx/IWDGf4xx.cpp
     src/core/dev/platform/f4xx/RTCf4xx.cpp
-    src/core/dev/platform/f4xx/Timerf4xx.cpp)
+    src/core/dev/platform/f4xx/Timerf4xx.cpp
+    src/core/io/SDRAM.cpp # STM32F469xx only peripheral
+    src/core/io/platform/f4xx/SDRAMf4xx.cpp)
 else()
     message(FATAL_ERROR "the HAL didnt compile in top level CMake")
 endif()

include/core/io/FMC.hpp

@@ -0,0 +1,105 @@
+#ifndef EVT_FMC_HPP
+#define EVT_FMC_HPP
+
+#include <core/io/GPIO.hpp>
+
+// #ifdef STM32F3xx
+//     #error Controlling SDRAM through an FMC is not supported on F3xx chips
+// #endif
+
+namespace core::io {
+
+/**
+ * The FMC is a Flexible Memory Controller used for controlling various forms of memory, including external SDRAM,
+ * NOR flash, NAND flash, and SRAM, the F3 series chips only support SRAM.
+ */
+class FMC {
+public:
+    /**
+     * Represents the status of operation of the FMC
+     *
+     * This can be used to represent the state of the SDRAM or the
+     * result of an FMC operation.
+     */
+    enum class Status {
+        OK      = 0x00U,
+        ERROR   = 0x01U,
+        BUSY    = 0x02U,
+        TIMEOUT = 0x03U,
+    };
+
+    /**
+     * Structure to hold an array of GPIO address pins for the FMC
+     */
+    struct FMCAddressPins {
+        Pin* pins;
+        uint8_t count;
+    };
+
+    /**
+     * Structure to hold an array of GPIO address pins for the FMC
+     */
+    struct FMCDataPins {
+        Pin* pins;
+        uint8_t count;
+    };
+
+    /**
+     * Structure to hold an array of GPIO command pins for the FMC
+     */
+    struct FMCCommandPins {
+        Pin* pins;
+        uint8_t count;
+    };
+
+    /**
+     * Structure to hold an array of GPIO byte enable pins for the FMC
+     */
+    struct FMCByteEnablePins {
+        Pin* pins;
+        uint8_t count;
+    };
+
+    /**
+     * Structure to hold an array of GPIO bank pins for the FMC
+     */
+    struct FMCBankPins {
+        Pin* pins;
+        uint8_t count;
+    };
+
+    /**
+     * Groups all FMC GPIO pin configurations.
+     *
+     * Contains arrays of:
+     * - Address pins
+     * - Data pins
+     * - Bank select pins
+     * - Command pins
+     * - Byte enable pins
+     */
+    struct FMCPinConfig {
+        FMCAddressPins address;
+        FMCDataPins data;
+        FMCByteEnablePins byteEnable;
+        FMCBankPins bank;
+        FMCCommandPins command;
+    };
+
+    /**
+     * Initializes an FMC device for controlling memory
+     */
+    FMC(void* memoryAddress, const FMCPinConfig& pinConfig);
+
+    virtual ~FMC() = default;
+
+    [[nodiscard]] void* getStartingAddress() const;
+
+protected:
+    FMCPinConfig fmcPinConfig;
+    void* memoryAddress;
+};
+
+} // namespace core::io
+
+#endif // EVT_FMC_HPP

include/core/io/SDRAM.hpp

@@ -0,0 +1,171 @@
+#ifndef EVT_SDRAM_HPP
+#define EVT_SDRAM_HPP
+
+#ifdef STM32F4xx
+    #include <HALf4/stm32f4xx_hal.h>
+    #include <core/io/FMC.hpp>
+
+/**
+ * SDRAM Command Mode
+ */
+constexpr uint32_t SDRAM_CMD_NORMAL_MODE      = 0x00000000U;
+constexpr uint32_t SDRAM_CMD_CLK_ENABLE       = 0x00000001U;
+constexpr uint32_t SDRAM_CMD_PALL             = 0x00000002U;
+constexpr uint32_t SDRAM_CMD_AUTOREFRESH_MODE = 0x00000003U;
+constexpr uint32_t SDRAM_CMD_LOAD_MODE        = 0x00000004U;
+constexpr uint32_t SDRAM_CMD_SELFREFRESH_MODE = 0x00000005U;
+constexpr uint32_t SDRAM_CMD_POWERDOWN_MODE   = 0x00000006U;
+
+/**
+ * SDRAM Command Target
+ */
+constexpr uint32_t SDRAM_CMD_TARGET_BANK2   = FMC_SDCMR_CTB2;
+constexpr uint32_t SDRAM_CMD_TARGET_BANK1   = FMC_SDCMR_CTB1;
+constexpr uint32_t SDRAM_CMD_TARGET_BANK1_2 = 0x00000018U;
+
+namespace core::io {
+
+/**
+ * Interface for configuring and accessing external SDRAM via FMC.
+ * Provides clock frequency functions
+ */
+class SDRAM : public FMC {
+public:
+    /**
+     * Holds all SDRAM controller settings that map directly to
+     * the HAL_SDRAM_Init configuration structure.
+     *
+     * Must be initialized before passing into the constructor
+     */
+    struct SDRAMInitConfig {
+        uint32_t sdBank;
+        uint32_t columnBitsNumber;
+        uint32_t rowBitsNumber;
+        uint32_t memoryDataWidth;
+        uint32_t internalBankNumber;
+        uint32_t casLatency;
+        uint32_t writeProtection;
+        uint32_t sdClockPeriod;
+        uint32_t readBurst;
+        uint32_t readPipeDelay;
+    };
+
+    /**
+     * Structure to simplify SDRAM timing initialization, contains all required SDRAM timing delays in clock cycles.
+     *
+     * Must be initialized before passing into the constructor
+     */
+    struct SDRAMTimingConfig {
+        uint32_t loadToActiveDelay;
+        uint32_t exitSelfRefreshDelay;
+        uint32_t selfRefreshTime;
+        uint32_t rowCycleDelay;
+        uint32_t writeRecoveryTime;
+        uint32_t rpDelay;
+        uint32_t rcdDelay;
+    };
+
+    /**
+     * Structure to send commands to the SDRAM through the FMC
+     *
+     * CommandMode is the mode of the command, cam be a value from the SDRAM Command Mode #define group
+     * CommandTarget specifies which device to send the command to, cam be a value from the SDRAM Command Target #define
+     * group AutoRefreshNumber defines the number of consecutive auto refresh command issued in auto refresh mode, can
+     * be a value between 1 and 15 ModeRegisterDefinition defines the SDRAM Mode to register content
+     */
+    struct SDRAMCommandStruct {
+        uint32_t CommandMode;
+        uint32_t CommandTarget;
+        uint32_t AutoRefreshNumber;
+        uint32_t ModeRegisterDefinition;
+    };
+
+    /**
+     * Constructor for initializing an FMC to control external SDRAM
+     *
+     * @param sdramMemoryAddress
+     * @param pinConfig
+     * @param sdramInitConfig
+     * @param sdramTimingConfig
+     */
+    SDRAM(void* sdramMemoryAddress, const FMCPinConfig& pinConfig, const SDRAMInitConfig& sdramInitConfig,
+          const SDRAMTimingConfig& sdramTimingConfig);
+
+    /**
+     *
+     * @return the SDRAM clock frequency
+     */
+    static uint32_t getSdramClockFrequency();
+
+    /**
+     *
+     * @return the SDRAM clock period in microseconds
+     */
+    static uint32_t getSdramClockPeriodPS();
+
+    /**
+     *
+     * @return the SDRAM clock period in nanoseconds
+     */
+    static uint32_t NSToSdramClockCycles(uint32_t nanoseconds);
+
+    /**
+     * Enable write protection for the sdram
+     *
+     * @return the result of attempting to enable the write protection
+     */
+    virtual Status WriteProtectionEnable() = 0;
+
+    /**
+     * Disable write protection for the sdram
+     *
+     * @return the result of attempting to disable the write protection
+     */
+    virtual Status WriteProtection_Disable() = 0;
+
+    /**
+     * Send a command to the sdram
+     *
+     * @param command The SdramCommandStruct holding the information of the command
+     * @param timeout How long to wait for the sdram command
+     * @return the result of attempting to send a command to the sdram
+     */
+    virtual Status SendCommand(SDRAMCommandStruct* command, uint32_t timeout) = 0;
+
+    /**
+     * Program the SDRAM Memory Refresh rate.
+     *
+     * @param refreshRate The SDRAM refresh rate value
+     * @return the result of attempting to program the refresh rate of the sdram
+     */
+    virtual Status ProgramRefreshRate(uint32_t refreshRate) = 0;
+
+    /**
+     * Set the Number of consecutive SDRAM Memory auto Refresh commands.
+     *
+     * @param autoRefreshNumber Specifies the auto Refresh number.
+     * @return
+     */
+    virtual Status SetAutoRefreshNumber(uint32_t autoRefreshNumber) = 0;
+
+    /**
+     * Returns the indicated FMC SDRAM bank mode status.
+     *
+     * @return The FMC SDRAM bank mode status, could be on of the following HAL defines:
+     *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
+     *         FMC_SDRAM_POWER_DOWN_MODE.
+     */
+    virtual uint32_t GetModeStatus() = 0;
+
+    // void* sdramMemoryAddress;
+
+protected:
+    SDRAMInitConfig sdramInitConfig;
+    SDRAMTimingConfig sdramTimingConfig;
+};
+
+} // namespace core::io
+
+#endif // STM32F4xx
+
+#endif // EVT_SDRAM_HPP