Add TI MSP DMA Support for MSPM33 Platform #7
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padmaraghunathan90 merged 6 commits intodev_mspm33from Jan 23, 2026
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Addressed all the comments given by @Shreyas-Shankar155 and pushed the changes
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Add DMA driver binding for Texas Instruments MSP Family series Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
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| source ~/zephyrproject/zephyr/zephyr-env.sh | ||
| west build -p always -b lp_mspm33c321a samples/basic/blinky | ||
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| - name: Build ADC Sequence example |
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HSADC has changed a lot during SDK APL release and that's why the sample is not building. So needs to inculcate those changes in the drivers
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Add DMA driver support for Texas Instruments MSP family series Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Add DMA nodes to the dtsi for TI MSPM33 Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Add DMA test driver support for Texas Instrument's lp_mspm33c321a launchpad Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Temporary removing ADC test case due to the changes made in the APL release of SDK for ADC Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
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ASM is notoriously harder to maintain than C and requires core specific adaptation which impairs even more the readability of the code. There's a bug in current arch_cpu_atomic_idle asm version: tst x0, #(DAIF_IRQ_BIT) //here Z := (DAIF_IRQ_BIT == 0) beq _irq_disabled //jump to _irq_disabled when Z is set msr daifclr, #(DAIFCLR_IRQ_BIT) _irq_disabled: ret As can be seen, the asm code jumps to _irq_disabled when Z is set, but per aarch64 architecture reference, DAIF_IRQ == 0 means the IRQ is unmasked, I.E enabled. So the asm logic here is wrong. I fixed this bug in C version. This shows the benefit of ASM -> C As for performance concern, except the bug fix above, there's no difference of generated code between ASM and C version. ASM version: <arch_cpu_idle>: d5033f9f dsb sy d503207f wfi d50342ff msr daifclr, #0x2 d65f03c0 ret arch_cpu_atomic_idle>: d50342df msr daifset, #0x2 d5033fdf isb d503205f wfe f279001f tst x0, #0x80 54000040 b.eq 1001d10 <_irq_disabled> // b.none d50342ff msr daifclr, #0x2 _irq_disabled>: d65f03c0 ret C version: <arch_cpu_idle>: d5033f9f dsb sy d503207f wfi d50342ff msr daifclr, #0x2 d65f03c0 ret <arch_cpu_atomic_idle>: d50342df msr daifset, #0x2 d5033fdf isb d503205f wfe 37380040 tbnz w0, #7, 1001d0c <arch_cpu_atomic_idle+0x14> d50342ff msr daifclr, #0x2 d65f03c0 ret And as can be seen, C version use the tbnz instruction to test bit and branch. Unlike TST, TBNZ does not affect the Z, N, C, or V flags in the processor state. So except the bug fix, C version looks a bit better than asm version. Other architectures such as x86, riscv, rx, xtensa, mips and even arm cortex_m also use c version for cpu_idle, it's safe for ASM -> C. Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
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This PR adds Direct Memory Access (DMA) support for the Texas Instruments MSP microcontrollers, specifically targeting the MSPM33 series.
Testing
The implementation has been verified with the following tests:
tests/drivers/dma/chan_blen_transfer- Validates basic DMA transfers with different block lengthstests/drivers/dma/loop_transfer- Tests continuous DMA loop transfersAll tests pass on the lp_mspm33c321a target board.
chan_blen_transfer test:
loop_transfer test: